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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 29
Volume 29, Number 1, January 2024
- Tianming Ni
, Xiaoqing Wen, Hussam Amrouch, Cheng Zhuo, Peilin Song:
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware. 1:1-1:3 - Yijun Cui, Jiang Li, Yunpeng Chen, Chenghua Wang, Chongyan Gu, Máire O'Neill, Weiqiang Liu:
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA. 2:1-2:20 - Taixin Li, Boran Sun, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Liang Shi, Tianyi Wang, Yao Yu, Thomas Kämpfe, Kai Ni, Huazhong Yang, Xueqing Li:
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories. 3:1-3:18 - Zijin Pan, Xunyu Li, Weiquan Hao, Runyu Miao, Albert Z. Wang:
On-chip ESD Protection Design Methodologies by CAD Simulation. 4:1-4:41 - Jingchang Bian, Zhengfeng Huang, Peng Ye, Zhao Yang, Huaguo Liang:
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations. 5:1-5:16 - Yuan Zhang, Jiliang Zhang:
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing. 6:1-6:19 - Dong Xiang:
Test Compression for Launch-on-Capture Transition Fault Testing. 7:1-7:20 - Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang:
AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems. 8:1-8:19 - Paul Calzada, Md Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM. 9:1-9:25 - Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui:
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. 10:1-10:21 - Jie Xiao, Yingying Ge, Ru Wang, Jungang Lou:
ICP-RL: Identifying Critical Paths for Fault Diagnosis Using Reinforcement Learning. 11:1-11:20 - Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, Xuan Zeng:
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation. 12:1-12:17 - Qingsong Peng, Jingchang Bian, Zhengfeng Huang, Senling Wang, Aibin Yan:
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. 13:1-13:17 - Rihui Sun, Pengfei Qiu, Yongqiang Lyu, Jian Dong, Haixia Wang, Dongsheng Wang, Gang Qu:
Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs. 14:1-14:22
- Enes Saglican, Engin Afacan:
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark. 15:1-15:23 - Martin Rapp, Heba Khdr, Nikita Krohmer, Jörg Henkel:
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores. 16:1-16:23 - Monzurul Islam Dewan, Sheng-En David Lin, Dae Hyun Kim:
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. 17:1-17:28 - Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. 18:1-18:25 - Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda:
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. 19:1-19:35 - Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. 20:1-20:23 - Wanqian Li, Yinhe Han, Xiaoming Chen:
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators. 21:1-21:24 - Dan Wu, Peng Chen, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra:
Flip: Data-centric Edge CGRA Accelerator. 22:1-22:25
- Ying Wu, Chuangtao Chen, Weihua Xiao, Xuan Wang, Chenyi Wen, Jie Han, Xunzhao Yin, Weikang Qian, Cheng Zhuo:
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits. 23:1-23:37
Volume 29, Number 2, March 2024
- Tung-Che Liang, Yi-Chen Chang, Zhanwei Zhong, Yaas Bigdeli, Tsung-Yi Ho, Krishnendu Chakrabarty, Richard B. Fair:
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips. 24:1-24:24 - Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang:
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. 25:1-25:33 - Bo Wang, Sheng Ma, Shengbai Luo, Lizhou Wu, Jianmin Zhang, Chunyuan Zhang, Tiejun Li:
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow. 26:1-26:32 - Jaspinder Kaur, Shirshendu Das:
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. 27:1-27:22 - Seok Young Kim, Jaewook Lee, Yoonah Paik, Chang Hyun Kim, Won Jun Lee, Seon Wook Kim:
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference. 28:1-28:22 - Linwei Niu, Danda B. Rawat, Jonathan Musselwhite, Zonghua Gu, Qingxu Deng:
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing. 29:1-29:35 - Newsha Ardalani, Saptadeep Pal, Puneet Gupta:
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. 30:1-30:20 - S. Deepanjali, Sk. Noor Mahammad:
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware. 31:1-31:29 - Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, Sung Kyu Lim:
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning. 32:1-32:17 - Libing Deng, Gang Zeng, Ryo Kurachi, Hiroaki Takada, Xiongren Xiao, Renfa Li, Guoqi Xie:
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking. 33:1-33:26 - Syam Sankar, Ruchika Gupta, John Jose, Sukumar Nandi:
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans. 34:1-34:25 - Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik:
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. 35:1-35:25 - Ke Tang, Lang Feng, Zhongfeng Wang:
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins. 36:1-36:18 - Karthik Somayaji Nanjangud Suryanarayana, Peng Li:
Pareto Optimization of Analog Circuits Using Reinforcement Learning. 37:1-37:14 - Danping Jiang, Zibin Dai, Yanjiang Liu, Zongren Zhang:
RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA. 38:1-38:24 - Jianfeng Wang, Zhonghao Chen, Jiahao Zhang, Yixin Xu, Tongguang Yu, Ziheng Zheng, Enze Ye, Sumitha George, Huazhong Yang, Yongpan Liu, Kai Ni, Vijaykrishnan Narayanan, Xueqing Li:
A Module-Level Configuration Methodology for Programmable Camouflaged Logic. 39:1-39:31
- Hansika Weerasena, Prabhat Mishra:
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey. 40:1-40:41
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