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ORCID27th ASP-DAC 2022: Taipei, Taiwan
- 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022. IEEE 2022, ISBN 978-1-6654-2135-5
- Guowei Chen, Xinyang Yu, Yue Wang, Tran Minh Quan, Naofumi Matsuyama, Takuya Tsujimura, Kiichi Niitsu
:
A 0.5 mm2 Ambient Light-Driven Solar Cell-Powered Biofuel Cell-Input Biosensing System with LED Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact Lens. 1-2 - Taikun Ma, Wei Deng, Haikun Jia, Yejun He, Baoyong Chi:
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array. 3-4 - Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. 5-6 - Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang:
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. 7-8 - Tiago D. Perez, Samuel Pagliarini:
A Side-Channel Hardware Trojan in 65nm CMOS with 2μW precision and Multi-bit Leakage Capability. 9-10 - Hongyu Fang, Milos Doroslovacki, Guru Venkataramani:
SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side Channels. 11-18 - Zihan Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang, Gang Qu, Dongsheng Wang:
CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper). 19-24 - Congcong Chen, Chaoqun Shen, Jiliang Zhang:
Lightweight and Secure Branch Predictors against Spectre Attacks. 25-30 - Md Tanvir Arafin:
Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges. 31-36 - Shuyuan Yu, Maliha Tasnim, Sheldon X.-D. Tan:
HEALM: Hardware-Efficient Approximate Logarithmic Multiplier with Reduced Error. 37-42 - Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano:
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. 43-49 - Chengrui Zhang, Yu Ma, Pingqiang Zhou:
Thermal-Aware Layout Optimization and Mapping Methods for Resistive Neuromorphic Engines. 50-55 - Hsin-Chuan Huang, Chi-Chun Liang, Qining Wang, Xing Huang, Tsung-Yi Ho, Chang-Jin Kim:
NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips. 56-61 - Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. 62-67 - Gerold Fink, Philipp Ebner, Sudip Poddar, Robert Wille:
Improving the Robustness of Microfluidic Networks. 68-73 - Sen Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang:
An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning. 74-79 - Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang:
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. 80-85 - Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou:
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. 86-91 - Ziwei Li, Han Xu, Zheyu Liu, Li Luo, Qi Wei, Fei Qiao:
A 2.17μW@120fps Ultra-Low-Power Dual-Mode CMOS Image Sensor with Senputing Architecture. 92-93 - Jiho Kim, Kwoanyoung Park, Tae-Hwan Kim:
A Reconfigurable Inference Processor for Recurrent Neural Networks Based on Programmable Data Format in a Resource-Limited FPGA. 94-95 - Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. 96-97 - Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. 98-99 - Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. 100-107 - Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). 108-113 - Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar:
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. 114-121 - Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang:
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. 122-127 - Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi:
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. 128-133 - Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression. 134-139 - Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, Deming Chen:
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. 140-146 - Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu:
Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines. 147-153 - Yue Xing, Aarti Gupta, Sharad Malik:
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. 154-159 - Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. 160-165 - Xuezhong Lin, Jingyu Pan, Jinming Xu, Yiran Chen, Cheng Zhuo:
Lithography Hotspot Detection via Heterogeneous Federated Learning with Local Adaptation. 166-171 - Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang:
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. 172-177 - Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang:
Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. 178-183 - Tai Yang, Guoqing He, Peng Cao:
Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework. 184-189 - Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
Efficient Critical Paths Search Algorithm using Mergeable Heap. 190-195 - Kai Wang, Peng Cao:
A Graph Neural Network Method for Fast ECO Leakage Power Optimization. 196-201 - Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chien-Mo James Li, Norman Chang, Ying-Shiun Li, Wentze Chuang:
Vector-based Dynamic IR-drop Prediction Using Machine Learning. 202-207 - Mohammadamir Kavousi, Liang Chen, Sheldon X.-D. Tan:
Fast Electromigration Stress Analysis Considering Spatial Joule Heating Effects. 208-213 - Febin Sunny, Mahdi Nikdast, Sudeep Pasricha:
SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep Learning. 214-219 - Jaeyoung Kang, Behnam Khaleghi, Yeseong Kim, Tajana Rosing:
XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training. 220-225 - Qidong Tang, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, Li Jiang:
HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine. 226-231 - Tianen Chen, Taylor Kemp, Younghyun Kim:
SYNTHNET: A High-throughput yet Energy-efficient Combinational Logic Neural Network. 232-237 - Zerun Li, Xiaoming Chen, Yinhe Han:
Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. 238-243 - Chongnan Ye, Chundong Wang:
Boosting the Search Performance of B+-tree with Sentinels for Non-volatile Memory. 244-249 - Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. 250-255 - Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen:
Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. 256-261 - Yuanbin Zhou, Soheil Samii, Petru Eles, Zebo Peng:
Time-Triggered Scheduling for Time-Sensitive Networking with Preemption. 262-267 - Hua Jiang, Raghav Chakravarthy, Ravikumar V. Chakaravarthy:
A Task Parallelism Runtime Solution for Deep Learning Applications using MPSoC on Edge Devices. 268-274 - Zishen Wan, Ashwin Sanjay Lele, Arijit Raychowdhury:
Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper). 275-280 - Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar:
RTL Regression Test Selection using Machine Learning. 281-287 - Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. 288-293 - Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang:
HybridGP: Global Placement for Hybrid-Row-Height Designs. 294-299 - Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan:
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. 300-306 - Chen Wang, Weikang Qian:
Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and Minimization. 307-313 - Yuhong Song, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Rui Xu, Yongzhuo Zhang, Bingzhe Li, Lei Yang:
BSC: Block-based Stochastic Computing to Enable Accurate and Efficient TinyML. 314-319 - Hsuan Hsiao, Joshua San Miguel, Jason Helge Anderson:
Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. 320-325 - Sooryaa Vignesh Thiruloga, Vipin Kumar Kukkala, Sudeep Pasricha:
TENET: Temporal CNN with Attention for Anomaly Detection in Automotive Cyber-Physical Systems. 326-331 - Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement. 332-338 - Xiaoming Chen, Yinhe Han:
Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique. 339-344 - Darayus Adil Patel, Viet Phuong Bui, Kevin Tshun Chuan Chai, Amit Lal, Mohamed M. Sabry Aly:
SonicFFT: A system architecture for ultrasonic-based FFT acceleration. 345-351 - Tashfia Alam, Zhenkun Yang, Bo Chen, Nicholas Armour, Sandip Ray:
FirVer: Concolic Testing for Systematic Validation of Firmware Binaries. 352-357 - Lucas Klemmer, Daniel Große:
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. 358-364 - Junhua Huang, Hui-Ling Zhen, Naixing Wang, Mingxuan Yuan, Hui Mao, Yu Huang, Jiping Tao:
Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics. 365-370 - Mohamed Saleh Abouelyazid, Sherif Hammouda, Yehea Ismail:
A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning. 371-376 - Jiacheng Huang, Min Peng, Libing Wu, Chun Jason Xue, Qingan Li:
Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail. 377-382 - Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang:
Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. 383-388 - Rui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin:
Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding. 389-394 - Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli:
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. 395-402 - Ulrich Brenner, Anna Silvanus:
Delay Optimization of Combinational Logic by AND-OR Path Restructuring. 403-409 - Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli:
A Versatile Mapping Approach for Technology Mapping and Graph Optimization. 410-416 - Prithwish Basu Roy, Patanjali SLPSK, Chester Rebeiro:
Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault Transformations. 417-422 - Mariam Tlili, Alhassan Sayed, Doaa Mahmoud, Marie-Minerve Louërat, Hassan Aboushady, Haralampos-G. Stratigopoulos:
Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI. 423-428 - Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. 429-435 - Chen Tang, Wenyu Sun, Wenxun Wang, Yongpan Liu:
Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning. 436-441 - Yixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu:
Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation. 442-447 - Liuyao Dai, Quan Cheng, Yuhang Wang, Gengbin Huang, Junzhuo Zhou, Kai Li, Wei Mao, Hao Yu:
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks. 448-453 - Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar:
Multi-Precision Deep Neural Network Acceleration on FPGAs. 454-459 - Fereshte Mozafari, Yuxiang Yang, Giovanni De Micheli:
Efficient Preparation of Cyclic Quantum States. 460-465 - Lukas Burgholzer, Sarah Schneider, Robert Wille:
Limiting the Search Space in Optimal Quantum Circuit Mapping. 466-471 - Akash Levy, Michael Oduoza, Akhilesh Balasingam, Roger T. Howe, Priyanka Raina:
Efficient Routing in Coarse-Grained Reconfigurable Arrays Using Multi-Pole NEM Relays. 472-478 - Kangwei Xu, Yuanqing Cheng:
Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs. 479-484 - Liang Chen, Wentian Jin, Sheldon X.-D. Tan:
Fast Thermal Analysis for Chiplet Design based on Graph Convolution Networks. 485-492 - Hussam Amrouch, Florian Klemme, Paul R. Genssler:
Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired Algorithms. 493-499 - Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan:
Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). 500-505 - Felix Last, Ceren Yeni, Ulf Schlichtmann:
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level. 506-512 - Naomi Sagan, Jaijeet Roychowdhury:
Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate Formulation. 513-518 - Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan:
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. 519-525 - Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. 526-531 - Abhinav Goel, Caleb Tung, Xiao Hu, George K. Thiruvathukal, James C. Davis, Yung-Hsiang Lu:
Efficient Computer Vision on Edge Devices with Pipeline-Parallel Hierarchical Neural Networks. 532-537 - Ze-Han Wang, Zhenli He, Hui Fang, Yi-Xiong Huang, Ying Sun, Yu Yang, Zhi-Yuan Zhang, Di Liu:
Efficient On-Device Incremental Learning by Weight Freezing. 538-543 - Maedeh Hemmat, Azadeh Davoodi, Yu Hen Hu:
$\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency. 544-549 - Andrea Damiani, Emanuele Del Sozzo, Marco D. Santambrogio:
Large Forests and Where to "Partially" Fit Them. 550-555 - Shuyue Lan, Zhilu Wang, John Mamish, Josiah D. Hester, Qi Zhu:
AdaSens: Adaptive Environment Monitoring by Coordinating Intermittently-Powered Sensors. 556-561 - Wen Zhang, Tao Liu, Mimi Xie, Longzhuang Li, Dulal C. Kar, Chen Pan:
Energy Harvesting Aware Multi-Hop Routing Policy in Distributed IoT System Based on Multi-Agent Reinforcement Learning. 562-567 - Lingxiao Hou, Yutaka Masuda, Tohru Ishihara:
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. 568-573 - Yilan Li, Haowen Fang, Mingyang Li, Yue Ma, Qinru Qiu:
Neural Network Pruning and Fast Training for DRL-based UAV Trajectory Planning. 574-579 - Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang:
High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. 580-585 - Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali:
SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity. 586-591 - Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang:
FPGA-Accelerated Maze Routing Kernel for VLSI Designs. 592-597 - Anlan Yu, Ning Lyu, Wujie Wen, Zhiyuan Yan:
Reliable Memristive Neural Network Accelerators Based on Early Denoising and Sparsity Induction. 598-603 - Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing:
Boosting ReRAM-based DNN by Row Activation Oversubscription. 604-609 - Fan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan:
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption. 610-615 - Rami Beidas, Jason Helge Anderson:
CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. 616-622 - M. Imtiaz Rashid, Benjamin Carrión Schäfer:
Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. 623-628 - Benjamin Carrión Schäfer:
Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling. 629-634 - Hao Geng, Tinghuan Chen, Qi Sun, Bei Yu:
Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper). 635-640 - Yufei Chen, Haojie Pei, Xiao Dong, Zhou Jin, Cheng Zhuo:
Application of Deep Learning in Back-End Simulation: Challenges and Opportunities. 641-646 - Jiaxi Zhang, Qiuyang Gao, Yijiang Guo, Bizhao Shi, Guojie Luo:
EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). 647-653 - Pengfei Qiu, Dongsheng Wang, Yongqiang Lyu, Gang Qu:
DVFSspy: Using Dynamic Voltage and Frequency Scaling as a Covert Channel for Multiple Procedures. 654-659 - A. V. Lakshmy, Chester Rebeiro, Swarup Bhunia:
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs. 660-665 - Jonas Krautter, Mahta Mayahinia, Dennis R. E. Gnad, Mehdi B. Tahoori:
Data Leakage through Self-Terminated Write Schemes in Memristive Caches. 666-671 - Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. 672-677 - Rui Liu, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang:
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. 678-683 - Yuxuan Huang, Yifan He, Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. 684-689 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Fan Yao, Rickard Ewetz:
STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing. 690-695 - Swantje Plambeck, Lutz Schammer, Görschwin Fey:
On the Viability of Decision Trees for Learning Models of Systems. 696-701 - Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai:
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. 702-707 - Hao Kong, Di Liu, Xiangzhong Luo, Weichen Liu, Ravi Subramaniam:
HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs. 708-713 - Arko Dutt, Suprojit Nandy, Mohamed M. Sabry:
Pearl: Towards Optimization of DNN-accelerators Via Closed-Form Analytical Representation. 714-719
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