IEEE Design & Test of Computers, Volume 20

Volume 20, Number 1, January/February 2003

EIC Message

• 
  Rajesh Gupta:
  From the Editor in Chief: Twenty years! IEEE Des. Test Comput. 20(1): 1- (2003)

Features

• 
  Alex Orailoglu, Alexander V. Veidenbaum:
  Guest Editors' Introduction: Application-Specific Microprocessors. IEEE Des. Test Comput. 20(1): 6-7 (2003)
• 
  Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer:
  A 100-GOPS Programmable Processor for Vehicle Vision Systems. 8-16
• 
  Peter Petrov, Alex Orailoglu:
  Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. 18-25
• 
  Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt:
  Compilation Approach for Coarse-Grained Reconfigurable Architectures. 26-33
• 
  Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr:
  Instruction Scheduler Generation for Retargetable Compilation. 34-41

Special Features

• 
  Jörg E. Vollrath:
  Testing and Characterization of SDRAMs. 42-50
• 
  Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
  2D Test Sequence Generators. 51-59
• 
  Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei:
  An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. 60-67
• 
  Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne:
  Design Techniques for EEPROMs Embedded in Portable Systems on Chips. 68-75
• 
  Luigi Carro, Marcelo Negreiros, Gabriel Parmegiani Jahn, Adão Antônio de Souza Jr., Denis Teixeira Franco:
  Circuit-Level Considerations for Mixed-Signal Programmable Components. 76-84

The Road Ahead

• 
  Andrew B. Kahng:
  Error Tolerance. IEEE Des. Test Comput. 20(1): 86-87 (2003)

Panel Summarie

• 
  Carol Stolicny:
  ITC 2002 Panels. IEEE Des. Test Comput. 20(1): 88-90 (2003)

Standards

• 
  Peter J. Ashenden:
  Boundary Scan Test Standards. IEEE Des. Test Comput. 20(1): 91-92 (2003)

Conference Reports

• 
  Ahmed Amine Jerraya:
  Hot Topics at HLDVT 02. IEEE Des. Test Comput. 20(1): 92- (2003)

Newsletters

• 
  DATC Newsletter. IEEE Des. Test Comput. 20(1): 93- (2003)
• 
  TTTC Newsletter. IEEE Des. Test Comput. 20(1): 94-95 (2003)

The Last Byte

• 
  Frank Vahid:
  Making the Best of Those Extra Transistors. IEEE Des. Test Comput. 20(1): 96- (2003)

Volume 20, Number 2, March/April 2003

EIC Message

• 
  Rajesh Gupta:
  From the Editor in Chief: Full Circle? IEEE Des. Test Comput. 20(2): 1- (2003)

Features

• 
  Monica Lobetti Bodoni, Ben Bennetts:
  Guest Editors' Introduction: Board Test. 5-7
• 
  Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts:
  Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. 8-18
• 
  Bradford G. Van Treuren, José M. Miranda:
  Embedded Boundary Scan. 20-25
• 
  Mahnaz Salamati, Dag Stranneby:
  Electromagnetic Signatures as a Tool for Connectionless Test. 26-30
• 
  Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell:
  Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. 32-39

Special Features

• 
  Nur Engin, Hans G. Kerkhoff:
  Fast Fault Simulation for Nonlinear Analog Circuits. 40-47
• 
  Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou:
  A Design-for-Verification Technique for Functional Pattern Reduction. 48-55
• 
  Miroslav Cupák, Francky Catthoor, Hugo De Man:
  Efficient System-Level Functional Verification Methodology for Multimedia Applications. 56-64
• 
  João M. P. Cardoso, Horácio C. Neto:
  Compilation for FPGA-Based Reconfigurable Hardware. 65-75

Round Table

• 
  Test Data Compression. IEEE Des. Test Comput. 20(2): 76-87 (2003)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 20(2): 88-89 (2003)

Panel Summaries

• 
  Carol Stolicny:
  ITC 2002 Panels: Part 2. IEEE Des. Test Comput. 20(2): 90-91 (2003)

Newsletters

• 
  DATC Newsletter. IEEE Des. Test Comput. 20(2): 93- (2003)
• 
  TTTC Newsletter. IEEE Des. Test Comput. 20(2): 94-95 (2003)

The Last Byte

• 
  Kenneth P. Parker:
  Testing for what? IEEE Des. Test Comput. 20(2): 96- (2003)

Volume 20, Number 3, May/June 2003

EIC Message

• 
  Rajesh Gupta:
  From the Editor in Chief: A "Powerful" Issue! IEEE Des. Test Comput. 20(3): 1- (2003)

Features

• 
  Sani R. Nassif, Soha Hassoun:
  Guest Editors' Introduction: On-Chip Power Distribution Networks. IEEE Des. Test Comput. 20(3): 5-6 (2003)
• 
  Sachin S. Sapatnekar, Haihua Su:
  Analysis and Optimization of Power Grids. 7-15
• 
  Rajendran Panda, Savithri Sundareswaran, David T. Blaauw:
  Impact of Low-Impedance Substrate on Power Supply Integrity. 16-22
• 
  Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
  Electrical Modeling of Integrated-Package Power and Ground Distributions. 24-31
• 
  Arindam Mukherjee, Malgorzata Marek-Sadowska:
  Clock and Power Gating with Timing Closure. 32-39
• 
  Ed Grochowski, David Ayers, Vivek Tiwari:
  Microarchitectural dI/dt Control. 40-47

Special Infrastructure IP Section

• 
  Yervant Zorian:
  Guest Editor's Introduction: Advances in Infrastructure IP. IEEE Des. Test Comput. 20(3): 49- (2003)
• 
  Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
  Online Self-Repair of FIR Filters. 50-57
• 
  Yervant Zorian, Samvel K. Shoukourian:
  Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. 58-66
• 
  Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta:
  Benefits of a SoC-Specific Test Methodology. 68-77
• 
  C. J. Clark, Mike Ricchetti:
  Infrastructure IP for Configuration and Test of Boards and Systems. 78-87

DAC Watch

• 
  Luciano Lavagno, Limor Fix:
  DAC Highlights. IEEE Des. Test Comput. 20(3): 88-89 (2003)
• 
  Alberto L. Sangiovanni-Vincentelli:
  DAC Turns 40! IEEE Des. Test Comput. 20(3): 90-96 (2003)
• 
  Pat O. Pistilli:
  DAC: Serving the EDA Community for 40 Years. IEEE Des. Test Comput. 20(3): 97-98 (2003)
• 
  Ronald A. Rohrer:
  DAC, Moore's Law Still Drive EDA. IEEE Des. Test Comput. 20(3): 99-100 (2003)
• 
  Giovanni De Micheli:
  CASS Brings Publishing to Its DAC Partnership. IEEE Des. Test Comput. 20(3): 101-102 (2003)

Special Report: CADathlon

• 
  Soha Hassoun, Geert Janssen:
  First CADathlon Programming Contest held at 2002 ICCAD. IEEE Des. Test Comput. 20(3): 104-107 (2003)

DTAP Update

• 
  Yervant Zorian:
  IEEE CASS becomes D&T Copublisher. IEEE Des. Test Comput. 20(3): 108- (2003)

The Road Ahead

• 
  Andrew B. Kahng:
  Bringing down NRE. IEEE Des. Test Comput. 20(3): 110-111 (2003)

Standards

• 
  Peter J. Ashenden:
  VHDL-200X: The Next Revision. IEEE Des. Test Comput. 20(3): 112-113 (2003)

Panel Summaries

• 
  Tom Anderson:
  Who Cares about System Verification? IEEE Des. Test Comput. 20(3): 114- (2003)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 20(3): 115- (2003)

Newsletters

• 
  TTTC Newsletter. IEEE Des. Test Comput. 20(3): 116-117 (2003)
• 
  DATC Newsletter. IEEE Des. Test Comput. 20(3): 118- (2003)

The Last Byte

• 
  Mary Jane Irwin:
  Power-Aware Designers at Odds with Power Grid Designers? IEEE Des. Test Comput. 20(3): 120- (2003)

Volume 20, Number 4, July/August 2003

EIC Message

• 
  Rajesh Gupta:
  From the Editor in Chief: Addressing Problems of the Large. 3

Special Features

• 
  Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas:
  A Practical Methodology for Verifying Pipelined Microarchitectures. 4-14
• 
  João Marques-Silva, Luís Guerra e Silva:
  Solving Satisfiability in Combinational Circuits. 16-21
• 
  Ozgur Sinanoglu, Alex Orailoglu:
  Compacting Test Responses for Deeply Embedded SoC Cores. 22-30
• 
  Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian:
  A Hierarchical Infrastructure for SoC Test Management. 32-39
• 
  Ian G. Harris:
  Fault Models and Test Generation for Hardware-Software Covalidation. 40-47
• 
  Nicola Nicolici, Bashir M. Al-Hashimi:
  Power-Conscious Test Synthesis and Scheduling. 48-55
• 
  Dionisios N. Pnevmatikatos, Ioannis Sourdis, Kyriakos Vlachos:
  An Efficient, Low-Cost I/O Subsystem for Network Processors. 56-64

Roundtable

• 
  Embedded Memories for the Future. IEEE Des. Test Comput. 20(4): 66-81 (2003)

Standards

• 
  David I. Rich:
  The Evolution of SystemVerilog. IEEE Des. Test Comput. 20(4): 82-84 (2003)

Panel Summaries

• 
  Carl Pixley, Juan Antonio Carballo:
  Panel Summaries. IEEE Des. Test Comput. 20(4): 86-88 (2003)

Conference Reports

• 
  McCluskey Awarded TTTC Lifetime Contribution Medal. IEEE Des. Test Comput. 20(4): 89- (2003)

Newsletters

• 
  TTTC Newsletter. IEEE Des. Test Comput. 20(4): 90-91 (2003)
• 
  DATC Newsletter. IEEE Des. Test Comput. 20(4): 93- (2003)

The Last Byte

• 
  Bill Mann:
  Test's Evolving Mission. IEEE Des. Test Comput. 20(4): 95-96 (2003)

Volume 20, Number 5, September/October 2003

From the EIC

• 
  Rajesh Gupta:
  At-Speed Testing: A Shared Red Brick between Design and Test. 1

Feature

• 
  Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang:
  Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. 6-7
• 
  Kee Sup Kim, Subhasish Mitra, Paul G. Ryan:
  Delay Defect Characteristics and Testing Strategies. 8-16
• 
  Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli:
  High-Frequency, At-Speed Scan Testing. 17-25
• 
  Stephen Pateras:
  Achieving At-Speed Structural Test. 26-33
• 
  Alfred L. Crouch, John C. Potter, Jason Doege:
  AC Scan Path Selection for Physical Debugging. 34-40
• 
  Bruce Cory, Rohit Kapur, Bill Underwood:
  Speed Binning with Path Delay Test in 150-nm Technology. 41-45
• 
  Robert Madge, Brady Benware, W. Robert Daasch:
  Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs. 46-53

ITC Watch

• 
  Robert C. Aitken, Gordon W. Roberts:
  ITC 2003: Breaking Test Interface Bottlenecks. IEEE Des. Test Comput. 20(5): 54- (2003)
• 
  Gordon W. Roberts, Robert C. Aitken:
  ITC Highlights. IEEE Des. Test Comput. 20(5): 55-57 (2003)
• 
  Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian:
  Embedded Deterministic Test for Low-Cost Manufacturing. 58-66
• 
  Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater:
  An On-Chip Self-Repair Calculation and Fusing Methodology. 67-75
• 
  Bill Eklow, Carl Barnhart, Kenneth P. Parker:
  IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. 76-83
• 
  Peter C. Maxwell:
  Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings. 84-89
• 
  ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby. 90-93

Standards

• 
  Jay Lawrence:
  Orthogonality of Verilog Data Types and Object Kinds. IEEE Des. Test Comput. 20(5): 94-96 (2003)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 20(5): 97-99 (2003)

Newsletters

• 
  DATC Newsletter. IEEE Des. Test Comput. 20(5): 100- (2003)
• 
  TTTC Newsletter. IEEE Des. Test Comput. 20(5): 102-103 (2003)

The Last Byte

• 
  Scott Davidson:
  All I Know I Learned at ITC. IEEE Des. Test Comput. 20(5): 104- (2003)

Volume 20, Number 6, November/December 2003

From the EIC

• 
  Rajesh Gupta:
  From the EIC: The changing face of IC design and its industry. 1

Features

• 
  Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi:
  Guest Editors' Introduction: Clockless VLSI Systems. 5-8
• 
  Alain J. Martin, Mika Nyström, Catherine G. Wong:
  Three Generations of Asynchronous Microprocessors. 9-17
• 
  Stephen H. Unger:
  Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors. 18-24
• 
  Satish K. Bandapati, Scott C. Smith, Minsu Choi:
  Design and Characterization of Null Convention Self-Timed Multipliers. 26-36
• 
  Steve Masteller, Lief Sorenson:
  Cycle Decomposition in NCL. 38-43
• 
  Juha Plosila, Tiberiu Seceleanu, Pasi Liljeberg:
  Implementation of a Self-Timed Segmented Bus. 44-50
• 
  Woo Jin Kim, Yong-Bin Kim:
  Automating Wave-Pipelined Circuit Design. 51-58

Special Section: Perspectives in EDA

• 
  Alberto L. Sangiovanni-Vincentelli:
  The Tides of EDA. 59-75
• 
  Fabless or IDM? What the Future Holds for Both: An Interview with Cirrus Logic Chairman, Michael L. Hackworth. IEEE Des. Test Comput. 20(6): 76-85 (2003)
• 
  What Is the Next Implementation Fabric? IEEE Des. Test Comput. 20(6): 86-95 (2003)

The Road Ahead

• 
  Andrew B. Kahng:
  How much variability can designers tolerate? IEEE Des. Test Comput. 20(6): 96-97 (2003)

Standards

• 
  Wolfgang Roethig:
  New advanced library format standard approved. IEEE Des. Test Comput. 20(6): 98-99 (2003)

Panel Summaries

• 
  Eric Dupont, Grant Martin:
  Panel Summaries. IEEE Des. Test Comput. 20(6): 100-102 (2003)

Conference Reports

• 
  Vladimir Hahanov, Raimund Ubar:
  Conference Reports. IEEE Des. Test Comput. 20(6): 103- (2003)

Newsletters

• 
  Test Technology TC Newsletter. IEEE Des. Test Comput. 20(6): 104-105 (2003)
• 
  Design Automation Technical Committee Newsletter. IEEE Des. Test Comput. 20(6): 106- (2003)

Annual Index

• 
  2003 Annual Index IEEE Design & Test of Computers Volume 20. 108-119

The Last Byte

• 
  Suhwan Kim, Conrad H. Ziesler:
  A clockless future for systems on chip. IEEE Des. Test Comput. 20(6): 120- (2003)