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ORCIDMike Shuo-Wei Chen
Shuo-Wei Michael Chen
Person information
- affiliation: University of Southern California, USA
- affiliation: University of California, Berkeley, USA
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2020 – today
- 2024
[j30]Mike Shuo-Wei Chen
, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga:
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 59(1): 4-7 (2024)- [j29]Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen:
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits 59(1): 40-51 (2024) - [c55]Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta:
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE 2024: 1-2 - [c54]Mostafa M. Ayesh, Soumya Mahapatra, Ce Yang, Mike Shuo-Wei Chen:
5.3 A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS. ISSCC 2024: 92-94 - [c53]Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen:
A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. VLSI Technology and Circuits 2024: 1-2 - [c52]Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen:
Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c51]Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen:
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j28]Ce Yang, Shiyu Su, Mike Shuo-Wei Chen:
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits 58(5): 1201-1211 (2023) - [c50]Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen:
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC 2023: 1-2 - [c49]Shiyu Su, Qiaochu Zhang, Mike Shuo-Wei Chen:
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC 2023: 1-2 - [c48]Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen:
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC 2023: 213-216 - [c47]Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen:
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC 2023: 226-227 - 2022
- [j27]Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57(1): 80-89 (2022) - [j26]Shiyu Su, Mike Shuo-Wei Chen:
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits 57(3): 906-916 (2022) - [j25]Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. IEEE J. Solid State Circuits 57(12): 3757-3767 (2022) - [c46]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC 2022: 100-107 - [c45]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC 2022: 526-531 - [c44]Shiyu Su, Mike Shuo-Wei Chen:
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC 2022: 1-8 - [c43]Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen:
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC 2022: 1021-1026 - [c42]Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. ISSCC 2022: 160-162 - [c41]Mike Shuo-Wei Chen:
Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems. VLSI-DAT 2022: 1 - 2021
- [j24]Shiyu Su, Mike Shuo-Wei Chen:
A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits 56(7): 2018-2028 (2021) - [j23]Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. ACM Trans. Design Autom. Electr. Syst. 26(5): 38:1-38:22 (2021) - [c40]Rezwan A. Rasul, Mike Shuo-Wei Chen:
A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. CICC 2021: 1-2 - [c39]Aoyang Zhang, Mostafa M. Ayesh, Soumya Mahapatra, Mike Shuo-Wei Chen:
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement. CICC 2021: 1-2 - [c38]Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen:
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC 2021: 505-510 - [c37]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c36]Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany:
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC 2021: 178-179 - [c35]Aoyang Zhang, Ce Yang, Mostafa M. Ayesh, Mike Shuo-Wei Chen:
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency. ISSCC 2021: 364-366 - [c34]Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen:
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC 2021: 410-412 - [i2]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR abs/2112.07824 (2021) - [i1]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR abs/2112.07825 (2021) - 2020
- [j22]Jae-Won Nam, Mike Shuo-Wei Chen:
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. IEEE J. Solid State Circuits 55(3): 557-566 (2020) - [c33]Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen:
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD 2020: 118:1-118:9 - [c32]Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen:
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD 2020: 119:1-119:9 - [c31]Shiyu Su, Mike Shuo-Wei Chen:
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC 2020: 174-176 - [c30]Tzu-Fan Wu, Mike Shuo-Wei Chen:
16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS. ISSCC 2020: 262-264
2010 – 2019
- 2019
- [j21]Tzu-Fan Wu, Mike Shuo-Wei Chen:
A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing. IEEE J. Solid State Circuits 54(3): 623-635 (2019) - [j20]Aoyang Zhang, Mike Shuo-Wei Chen:
A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement. IEEE J. Solid State Circuits 54(4): 1017-1028 (2019) - [j19]Aoyang Zhang, Mike Shuo-Wei Chen:
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier. IEEE J. Solid State Circuits 54(12): 3452-3465 (2019) - [c29]Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. CICC 2019: 1-4 - [c28]Jae-Won Nam, Mike Shuo-Wei Chen:
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. CICC 2019: 1-4 - [c27]Aoyang Zhang, Mike Shuo-Wei Chen:
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency. ISSCC 2019: 74-76 - [c26]Shiyu Su, Mike Shuo-Wei Chen:
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits 2019: 20- - 2018
- [j18]Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53(6): 1765-1779 (2018) - [j17]Shiyu Su, Mike Shuo-Wei Chen:
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits 53(12): 3517-3527 (2018) - [c25]Mike Shuo-Wei Chen:
Evolutions of SAR ADC: From high resolution to high speed regime. CICC 2018: 1-86 - [c24]Tzu-Fan Wu, Mike Shuo-Wei Chen:
A 200MHz-BW 0.13mm2 62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS. CICC 2018: 1-4 - [c23]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. ISSCC 2018: 254-256 - [c22]Shiyu Su, Mike Shuo-Wei Chen:
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC 2018: 362-364 - [c21]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC 2018: 394-396 - [c20]Aoyang Zhang, Mike Shuo-Wei Chen:
A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency. VLSI Circuits 2018: 213-214 - 2017
- [j16]Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. IEEE J. Solid State Circuits 52(9): 2335-2349 (2017) - [j15]Mohsen Hassanpourghadi, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1354-1367 (2017) - [c19]Rezwan A. Rasul, Pedram Teimouri, Mike Shuo-Wei Chen:
A time multiplexed network architecture for large-scale neuromorphic computing. MWSCAS 2017: 1216-1219 - 2016
- [j14]Shiyu Su, Mike Shuo-Wei Chen:
A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 2963-2978 (2016) - [j13]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 3216-3230 (2016) - [j12]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1111-1122 (2016) - [j11]Jae-Won Nam, Mike Shuo-Wei Chen:
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1628-1638 (2016) - [j10]Tzu-Fan Wu, Sourya Dey, Mike Shuo-Wei Chen:
A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1639-1651 (2016) - [c18]Cheng-Ru Ho, Mike Shuo-Wei Chen:
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. ESSCIRC 2016: 213-216 - [c17]Cheng-Ru Ho, Mike Shuo-Wei Chen:
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. ISSCC 2016: 190-191 - [c16]Shiyu Su, Mike Shuo-Wei Chen:
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC 2016: 456-457 - [c15]Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j9]Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits 50(4): 896-907 (2015) - [c14]Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. CICC 2015: 1-4 - 2014
- [j8]Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze:
Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 8-23 (2014) - [c13]Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC 2014: 1-2 - 2013
- [c12]Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen:
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. CICC 2013: 1-4 - [c11]Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. CICC 2013: 1-4 - 2012
- [c10]Dylan Hand, Mike Shuo-Wei Chen:
A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter. GLOBECOM 2012: 3707-3712 - [c9]Mike Shuo-Wei Chen:
Overhead minimization techniques for digital phase-locked loop frequency synthesizer. MWSCAS 2012: 682-685 - 2011
- [c8]Shahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian J. Kaczynski, Sang-Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik S. Mehta, Masoud Zargari, David K. Su:
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. ISSCC 2011: 170-172 - 2010
- [j7]Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta:
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC. IEEE J. Solid State Circuits 45(12): 2819-2827 (2010) - [c7]Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta:
A calibration-free 800MHz fractional-N digital PLL with embedded TDC. ISSCC 2010: 472-473
2000 – 2009
- 2009
- [j6]Sundar G. Sankaran, Brian J. Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley:
Design and implementation of a CMO 802.11n SoC. IEEE Commun. Mag. 47(4): 134-143 (2009) - 2008
- [j5]Masoud Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley:
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. IEEE J. Solid State Circuits 43(12): 2882-2895 (2008) - [c6]Lalitkumar Nathawad, Masoud Zargari, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Sunetra Mendis, Andrew Chang, Steve H. Jen, David K. Su, Bruce A. Wooley:
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. ISSCC 2008: 358-359 - 2007
- [j4]Shuo-Wei Michael Chen, Robert W. Brodersen:
A Subsampling Radio Architecture for Ultrawideband Communications. IEEE Trans. Signal Process. 55(10): 5018-5031 (2007) - [c5]Andrew Fort, Mike Shuo-Wei Chen, Robert W. Brodersen, Claude Desset, Piet Wambacq, Leo Van Biesen:
Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. ICC 2007: 5769-5774 - 2006
- [j3]Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Stanley Wang, Jing Yang, Robert W. Brodersen:
Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j2]Shuo-Wei Michael Chen, Robert W. Brodersen:
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS. IEEE J. Solid State Circuits 41(12): 2669-2680 (2006) - [c4]Mike Shuo-Wei Chen, Robert W. Brodersen:
Digital Complex Signal Processing Techniques for Impulse Radio. GLOBECOM 2006 - [c3]Mike Shuo-Wei Chen, Robert W. Brodersen:
A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS. ISSCC 2006: 2350-2359 - 2005
- [j1]Mike Shuo-Wei Chen, Robert W. Brodersen:
A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling. IEICE Trans. Electron. 88-C(6): 1114-1121 (2005) - [c2]Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Jing Yang, Robert W. Brodersen:
Future wireless systems: UWB, 60GHz, and cognitive radios. CICC 2005: 793-796 - 2004
- [c1]Mike Shuo-Wei Chen, Robert W. Brodersen:
A subsampling UWB radio architecture by analytic signaling. ICASSP (4) 2004: 533-536
Coauthor Index
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