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ORCIDKaushik Gala
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2000 – 2009
- 2003
[j3]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
:
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 49-66 (2003)- [j2]Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1533-1544 (2003) - [c8]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276 - [c7]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 - 2002
- [j1]Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi:
Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 730-745 (2002) - [c6]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 - [c5]Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal:
Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28 - 2001
- [c4]Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao:
Inductance 101: Analysis and Design Issues. DAC 2001: 329-334 - 2000
- [c3]Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw:
On-chip inductance modeling and analysis. DAC 2000: 63-68 - [c2]David T. Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang:
On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80 - [c1]Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Fast Analysis and Optimization of Power/Ground Networks. ICCAD 2000: 477-480
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