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ORCIDASP-DAC 2004: Yokohama, Japan
- Masaharu Imai:
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004. IEEE Computer Society 2004, ISBN 0-7803-8175-0
Keynote address
- Rudy Lauwereins:
System level design technology for realizing an ambient intelligent environment. 1-3
Selected European activities in SoC low power design methodologies and research networking
- Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig:
Fast, predictable and low energy memory references through architecture-aware compilation. 4-11 - Wolfgang Nebel:
Predictable design of low power systems by pre-implementation estimation and optimization. 12-17 - Ahmed Amine Jerraya:
EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package. 18
Floorplanning
- Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
Abstraction and optimization of consistent floorplanning with pillar block constraints. 19-24 - Xuliang Zhang, Yoji Kajitani:
Space-planning: placement of modules with controlled empty area by single-sequence. 25-30 - Jacob R. Minz, Sung Kyu Lim:
Layer assignment for reliable system-on-package. 31-37 - Xiaoping Tang, Martin D. F. Wong
:
On handling arbitrary rectilinear shape constraint. 38-41 - Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
Robust fixed-outline floorplanning through evolutionary search. 42-44
Modeling for analog circuits
- Jian Wang, Jun Tao, Xuan Zeng, Charles C. Chiang, Dian Zhou:
Analog circuit behavioral modeling via wavelet collocation method with auto-companding. 45-50 - Ewout Martens, Georges G. E. Gielen:
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. 51-56 - Payam Heydari:
High-frequency noise in RF active CMOS mixers. 57-60 - Rasit Onur Topaloglu, Alex Orailoglu:
On mismatch in the deep sub-micron era - from physics to circuits. 62-67
Behavioral synthesis
- Deming Chen, Jason Cong:
Register binding and port assignment for multiplexer optimization. 68-73 - Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A thread partitioning algorithm in low power high-level synthesis. 74-79 - Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura:
Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. 80-85 - Hashem Hashemi Najaf-abadi:
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline. 86-91
Delay test and BIST
- Kai Yang, Kwang-Ting Cheng, Li-C. Wang:
TranGen: a SAT-based ATPG for path-oriented transition faults. 92-97 - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest path selection for delay test under process variation. 98-103 - Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu:
SRAM delay fault modeling and test algorithm development. 104-109 - Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri:
An efficient design of non-linear CA based PRPG for VLSI circuit testing. 110-112 - Andrew B. Kahng, Sherief Reda:
Combinatorial group testing methods for the BIST diagnosis problem. 113-116
Embedded tutorial + regular session: embedded szstem applications
- Yukikazu Nakamoto:
Toward mobile phone Linux. 117-124 - Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow:
Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. 125-130 - Alexander Maxiaguine, Simon Künzli, Samarjit Chakraborty, Lothar Thiele:
Rate analysis for streaming applications with on-chip buffer constraints. 131-136
Placement
- Mongkol Ekpanyapong, Sung Kyu Lim:
Performance-driven global placement via adaptive network characterization. 137-142 - Bernd Obermeier, Frank M. Johannes:
Temperature-aware global placement. 143-148 - Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. 149-154 - Keoncheol Shin, Taewhan Kim:
An integrated approach to timing-driven synthesis and placement of arithmetic circuits. 155-158 - Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao:
Layer assignment for crosstalk risk minimization. 159-162
RF design methodology
- Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi:
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. 163-168 - Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong:
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO. 169-174 - Praveen Ghanta, Zheng Li, Jaijeet S. Roychowdhury:
Analytical expressions for phase noise eigenfunctions of LC oscillators. 175-180 - Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra:
Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations. 181-185
Practical issues in logic synthesis
- Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura:
Timing optimization by replacing flip-flops to latches. 186-191 - Hiroyuki Higuchi, Yusuke Matsunaga:
Enhancing the performance of multi-cycle path analysis in an industrial setting. 192-197 - Noureddine Chabini, Wayne H. Wolf:
An approach for reducing dynamic power consumption in synchronous sequential digital designs. 198-204 - Yen-Te Ho, TingTing Hwang:
Low power design using dual threshold voltage. 205-208 - Chang Woo Kang, Ali Iranli, Massoud Pedram:
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs. 209-211
Effective test and diagnosis
- Ozgur Sinanoglu, Alex Orailoglu:
Efficient RT-level fault diagnosis methodology. 212-217 - Alexander Smith, Andreas G. Veneris, Anastasios Viglas:
Design diagnosis using Boolean satisfiability. 218-223 - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. 224-229 - Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase:
Test data compression technique using selective don't-care identification. 230-233 - Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan:
Re-configurable embedded core test protocol. 234-237
System-level design methodology
- C. Schulz-Key, Markus Winterholer, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel:
Object-oriented modeling and synthesis of SystemC specifications. 238-243 - Robertas Damasevicius, Vytautas Stuikys:
Application of UML for hardware design based on design process model. 244-249 - Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. 250-255 - Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada:
Design methodology for SoC arthitectures based on reusable virtual cores. 256-262
Advanced design and modeling techniques
- Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng:
A multiple level network approach for clock skew minimization with process variations. 263-268 - Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
Layout techniques for on-chip interconnect inductance reduction. 269-273 - Zhong Wang, Jianwen Zhu:
Piecewise quadratic waveform matching with successive chord iteration. 274-279 - Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou:
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. 280-283 - Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy:
Adaptive supply voltage technique for low swing interconnects. 284-287
Analog design and evaluation
- Kyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn:
A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. 288-291 - Jianhua Gan, Shouli Yan, Jacob A. Abraham:
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. 292-297 - Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
Jitter spectral extraction for multi-gigahertz signal. 298-303 - Quoc-Hoang Duong, Sang-Gug Lee:
A 35 dB-linear exponential function generator for VGA and AGC applications. 304-306 - Simon Cimin Li, Vincent Chia-Chang Lin:
A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique. 307-309
System design verification
- Miroslav N. Velev:
Efficient translation of boolean formulas to CNF in formal verification of microprocessors. 310-315 - Miroslav N. Velev:
Using positive equality to prove liveness for pipelined microprocessors. 316-321 - Samar Abdi, Daniel Gajski:
On deriving equivalent architecture model from system specification. 322-327 - Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou:
On compliance test of on-chip bus for SOC. 328-333
Opportunities with the open architecture test system
- Kazumi Hatayama, Rochit Rajsuman:
Opportunities with the open architecture test system. 334 - Rochit Rajsuman:
New opportunities with the open architecture test system. 335 - Yasumasa Nishimura:
Open architecture tester: what is a key issue of OAT? 336 - Srimat T. Chakradhar:
Open architecture test system: not why but when! 337-340 - Adi Merschon:
New opportunities with the open architecture test system. 341 - Dennis M. Petrich:
Signal integrity analysis in the open architecture. 342 - Tetsuo Tada:
Opportunities with the open architecture test system. 343
C-based design examples
- Kazutoshi Wakabayashi:
C-based behavioral synthesis and verification analysis on industrial design examples. 344-348 - Chris Sullivan, Alex Wilson, Stephen P. G. Chappell:
Using C based logic synthesis to bridge the productivity gap. 349-354
Buffered tree construction
- Cliff C. N. Sze, Jiang Hu, Charles J. Alpert:
A place and route aware buffered Steiner tree construction. 355-360 - Sampath Dechu, Zion Cien Shen, Chris C. N. Chu:
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. 361-366 - Jun Chen, Lei He:
Modeling of coplanar waveguide for buffered clock tree. 367-372
Power-aware approach for microprocessor design
- Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya:
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures. 373-379 - Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu:
Mixed-clock issue queue design for energy aware, high-performance cores. 380-383 - G. Surendra, Subhasis Banerjee, S. K. Nandy:
Power-performance trade-off using pipeline delays. 384-386 - Subhasis Banerjee, G. Surendra, S. K. Nandy:
Exploiting program execution phases to trade power and performance for media workload. 387-389 - Subhasis Bhattacharjee, Dhiraj K. Pradhan:
LPRAM: a low power DRAM with testability. 390-393
Analog layout techniques
- Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi:
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. 394-399 - Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi:
Hierarchical extraction and verification of symmetry constraints for analog layout automation. 400-405 - Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts. 406-411
Formal verification
- Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay:
Model checking on state transition diagram. 412-417 - Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
Efficient reachability checking using sequential SAT. 418-423 - Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Exploiting state encoding for invariant generation in induction-based property checking. 424-429
Routing methodology
- Xiaoping Tang, Martin D. F. Wong:
Tradeoff routing resource, runtime and quality in buffered routing. 430-433 - Noriyuki Miura, Naoki Kato, Tadahiro Kuroda:
Practical methodology of post-layout gate sizing for 15% more power saving. 434-437 - Chanseok Hwang, Massoud Pedram:
Interconnect design methods for memory design. 438-443 - Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang:
Optimal planning for mesh-based power distribution. 444-449
Exploration for advanced SoC design
- Yangdong Steve Deng, Wojciech Maly:
2.5D system integration: a design driven system implementation schema. 450-455 - Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms. 456-458 - Frank Kienle, Norbert Wehn:
Design methodology for IRA codes. 459-462
Embedded software
- Haobo Yu, Rainer Dömer, Daniel Gajski:
Embedded software generation from system level design languages. 463-468 - Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya:
Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. 469-474 - Aviral Shrivastava, Nikil D. Dutt:
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). 475-477 - Yoonseo Choi, Taewhan Kim:
Memory access driven storage assignment for variables in embedded system design. 478-481
RF modeling and design methodology
- Mitiko Miura-Mattausch:
MOSFET modeling for RF-CMOS design. 482-490 - Robert A. Mullen:
RF design methodologies bridging system-IC-module design. 491-498
Power grid analysis and design
- Haifeng Qian, Sachin S. Sapatnekar:
Hierarchical random-walk algorithms for power grid analysis. 499-504 - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. 505-510 - Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda:
Large-scale linear circuit simulation with an inversed inductance matrix. 511-516 - Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity. 517-522
University design contest
- Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Design of real-time VGA 3-D image sensor using mixed-signal techniques. 523-524 - Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen:
A bandwidth and memory efficient MPEG-4 shape encoder. 525-526 - Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. 527-528 - Kimihiro Nishio, Hiroo Yonezu, Shinya Sawa, Yuzo Furukawa:
Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision. 529-530 - Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch:
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. 531-532 - Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo:
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. 533-534 - Simon Cimin Li, Vincent Chia-Chang Lin:
A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique. 535-536 - Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi:
A small-area high-performance 512-point 2-dimensional FFT single-chip processor. 537-538 - Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui:
Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. 539-540 - Yoshihiro Utsurogi, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi:
A dual-band image-reject mixer for GPS with 64dB image rejection. 541-542 - Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch:
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. 543-544 - Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera:
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. 545-546 - Yi-Ming Wang, Jinn-Shyan Wang:
A reliable low-power fast skew-compensation circuit. 547-548 - Jun Ohta, Tetsuo Furumiya, David C. Ng, Akihiro Uehara, Keiichiro Kagawa, Takashi Tokuda, Masahiro Nunoshita:
A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor. 549-550 - Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. 551-552