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ORCIDIEEE Journal of Solid-State Circuits, Volume 56
Volume 56, Number 1, January 2021
- Friedel Gerfers
, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl:
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). 3-6 - Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. 7-18 - Hao Li, Ganesh Balamurugan, Taehwan Kim, Meer Sakib, Ranjeet Kumar, Haisheng Rong, James E. Jaussi, Bryan Casper:
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control. 19-29 - Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai:
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture. 30-42 - Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton:
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS. 43-54 - Tianyu Jia, Yuhao Ju, Jie Gu:
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. 55-65 - Jong-Hyeok Yoon, Arijit Raychowdhury:
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. 66-78 - Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. 79-97 - David Wolpert, Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Dinesh Kannambadi, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Ramon Bertran, Pradeep Bhadravati Parashurama, Dureseti Chidambarrao, Brandon Bruen, Alan P. Wagstaff, Eric Lukes, Sean M. Carey, Hunter F. Shi, Michael Romain, Paul Logsdon, Ishita Agarwal:
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. 98-111 - Chieh Chung, Chia-Hsiang Yang:
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots. 112-122 - Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. 123-135 - Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen:
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. 136-150 - Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang:
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. 151-164 - Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. 165-178 - Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. 179-187 - Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. 188-198 - Ki Chul Chun, Yong-Ki Kim, Yesin Ryu, Jaewon Park, Chi Sung Oh, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Jung-Bae Lee:
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. 199-211 - Chang-Kyo Lee, Hyung-Joon Chi, Jin-Seok Heo, Junghwan Park, Jin-Hun Jang, Dongkeon Lee, Jaehoon Jung, Dong-Hun Lee, Dae-Hyun Kim, Kihan Kim, Sang-Yun Kim, Dukha Park, Youngil Lim, Geuntae Park, Seungjun Lee, Seungki Hong, Dae-Hyun Kwon, Isak Hwang, Byongwook Na, Kyungryun Kim, Seouk-Kyu Choi, Hye-In Choi, Hangi-Jung, Wonil Bae, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. 212-224 - Toshiyuki Kouchi, Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Yasufumi Kajiyama, Yuri Terada, Sanad Bushnaq, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Yamamoto, Yuki Ishizaki, Yoko Deguchi, Atsushi Okuyama, Junichi Sato, Hiroki Yabe, Cynthia Hsu, Masahiro Yoshihara:
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs. 225-234 - Guoxiang Han, Tanbir Haque, Matthew Bajor, John Wright, Peter R. Kinget:
A Multi-Branch Receiver With Modulated Mixer Clocks for Concurrent Dual-Carrier Reception and Rapid Compressive-Sampling Spectrum Scanning. 235-253 - Ming Ding, Peng Zhang, Yuming He, Stefano Traferro, Minyoung Song, Hannu Korpela, Kenichi Shibata, Keisuke Ueda, Yao-Hong Liu, Christian Bachmann:
A Bluetooth 5 Transceiver With a Phase-Tracking RX and Its Corresponding Digital Baseband in 40-nm CMOS. 254-266 - Keng Chen, Luca Petruzzi, Ronald Hulfachor, Marvin Onabajo:
A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers. 267-276 - Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li:
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming. 277-286 - Hui Liu, Xinpeng Xing, Georges G. E. Gielen:
A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS. 287-297 - Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi:
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. 298-309 - Bahaa Radi, Mohammadreza Sanadgol Nezami, Mohammad Taherzadeh-Sani, Frederic Nabki, Michaël Ménard, Odile Liboiron-Ladouceur:
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End. 310-323 - Eric J. Carlson, Kai Strunz, Brian P. Otis:
Erratum to "A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting". 324
Volume 56, Number 2, February 2021
- Xiang Yi, Cheng Wang, Xibi Chen, Jinchen Wang, Jesús Grajal, Ruonan Han:
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture. 327-339 - Muhammad Ibrahim Wasiq Khan, Mohamed I. Ibrahim, Chiraag Shashikant Juvekar, Wanyeong Jung, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Ruonan Han:
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication. 340-354 - Qian Zhong, Wooyeol Choi, Kenneth K. O:
Terahertz Even-Order Subharmonic Mixer Using Symmetric MOS Varactors. 355-366 - Gholamreza Nikandish, Robert Bogdan Staszewski, Anding Zhu:
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement. 367-381 - Umut Çelik, Patrick Reynaert:
Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI. 382-391 - Kaituo Yang, Xiang Yi, Chirn Chye Boon, Zhipeng Liang, Guangyin Feng, Chenyang Li, Bei Liu:
A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation. 392-403 - Amir Bozorg, Robert Bogdan Staszewski:
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse. 404-415 - Po-Han Peter Wang, Patrick P. Mercier:
An Interference-Resilient BLE-Compatible Wake-Up Receiver Employing Single-Die Multi-Channel FBAR-Based Filtering and a 4-D Wake-Up Signature. 416-426 - Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski:
A Type-II Phase-Tracking Receiver. 427-439 - Nilan Udayanga, Arjuna Madanayake, S. I. Hariharan, Jifu Liang, Soumyajit Mandal, Leonid Belostotski, Len T. Bruton:
A Radio Frequency Analog Computer for Computational Electromagnetics. 440-454 - Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka:
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. 455-464 - Il-Min Yi, Naoki Miura, Hideyuki Nosaka:
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. 465-475 - Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun:
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. 476-487 - Jong-Seok Kim, Jin-O. Yoon, Byong-Deok Choi:
A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays. 488-500 - Sining Pan, Kofi A. A. Makinwa:
A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA. 501-510 - Feng Chen, Yasu Lu, Philip K. T. Mok:
A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS. 511-520 - Xugang Ke, Dong Yan, Joseph Sankman, Min Kyu Song, Dongsheng Ma:
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and VSW Dual-Edge Dead-Time Modulation Techniques. 521-530 - Yingping Chen, Dongsheng Ma:
A 10-MHz Closed-Loop EMI-Regulated GaN Switching Power Converter Using Emulated Miller Plateau Tracking and Adaptive Strength Gate Driving. 531-540 - Junyoung Maeng, Inho Park, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications. 541-553 - Hanwool Jeong, Tae Hyun Kim, Changnam Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. 554-565 - Cheng Wang, Xiang Yi, Mina Kim, Qingyu Ben Yang, Ruonan Han:
A Terahertz Molecular Clock on CMOS Using High-Harmonic-Order Interrogation of Rotational Transition for Medium-/Long-Term Stability Enhancement. 566-580 - Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim:
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. 581-590 - Nahmil Koo, SeongHwan Cho:
A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS. 591-600 - Benoît Labbé, Philex Ming-Yan Fan, Thanusree Achuthan, Pranay Prabhat, Graham Knight, James Myers:
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller. 601-611 - Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang:
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. 612-623 - Zhengyu Chen, Jie Gu:
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. 624-635 - Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang:
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. 636-647 - Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee:
A 354F2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security. 648-657 - Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. 658-673
Volume 56, Number 3, March 2021
- Qun Jane Gu, Mark S. Oude Alink:
Guest Editorial 2020 Custom Integrated Circuits Conference. 679-680 - Shenggang Dong, Ibukunoluwa Momson, Sandeep Kshattry, Pavan Yelleswarapu, Wooyeol Choi, Kenneth K. O:
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver. 681-693 - Dongyi Liao, Fa Foster Dai:
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation. 694-704 - Amr Ahmed, Min-Yu Huang, David Joseph Munzer, Hua Wang:
A 43-97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection. 705-714 - Arian Hashemi Talkhooncheh, You Yu, Abhinav Agarwal, William Wei-Ting Kuo, Kuan-Chang Xavier Chen, Minwo Wang, Gudrun Hoskuldsdottir, Wei Gao, Azita Emami:
A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT. 715-728 - Alok Baluni, Shanthi Pavan:
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback. 729-738 - Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun:
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. 739-749 - Kuan-Chang Xavier Chen, William Wei-Ting Kuo, Azita Emami:
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS. 750-762 - Ping-Hung Yin, Chih-Wen Lu, Jia-Shyang Wang, Keng-Li Chang, Fu-Kuo Lin, Poki Chen:
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs. 763-777 - Marco Croce, Brian Friend, Francesco Nesta, Lorenzo Crespi, Piero Malcovati, Andrea Baschirotto:
A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment. 778-787 - Shovan Maity, Nirmoy Modak, David Yang, Mayukh Nath, Shitij Avlani, Debayan Das, Josef Danial, Parikha Mehrotra, Shreyas Sen:
Sub-μWRComm: 415-nW 1-10-kb/s Physically and Mathematically Secure Electro-Quasi-Static HBC Node for Authentication and Medical Applications. 788-802 - Minkyu Kim, Jae-Sun Seo:
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. 803-813 - Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. 814-823 - Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw:
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. 824-833 - Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher Rozell, Justin Romberg, Michael P. Flynn:
A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. 834-843 - Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee:
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. 844-854 - Chen Chen, Jin Liu, Hoi Lee:
A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter. 855-865 - Yanqiao Li, Benjamin L. Dobbins, Jason T. Stauth:
An Optically Powered, High-Voltage, Switched- Capacitor Drive Circuit for Microrobotics. 866-875 - Yijie Wei, Qiankai Cao, Kofi Otseidu, Levi J. Hargrove, Jie Gu:
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. 876-886 - Jaehyuk Lee, Surin Gweon, Kwonjoon Lee, Soyeon Um, Kyoung-Rog Lee, Hoi-Jun Yoo:
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection. 887-898 - Maciej Kucharski, Wael Abdullah Ahmad, Herman Jalli Ng, Dietmar Kissinger:
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation. 899-913 - Alireza Asoodeh, Hossein Miri Lavasani, Mengye Cai, Shahriar Mirabbasi:
A Highly Linear and Efficient 28-GHz PA With a Psat of 23.2 dBm, P1 dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS. 914-927 - Shi Bu, Sameed Hameed, Sudhakar Pamarti:
Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends. 928-939 - Hayun Chung, Minji Hyun, Jungwon Kim:
A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS. 940-949 - Zhaoyang Yin, Yibing Michelle Wang, Eric R. Fossum:
Low Bit-Depth ADCs for Multi-bit Quanta Image Sensors. 950-960 - Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Dongju Lim, Chulwoo Kim:
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode. 961-971 - Abishek Manian, Amit Rane, Yongseon Koh, Harsheen Kaur Nat, Michael Lu:
A Simultaneous Bidirectional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s Back Channels. 972-987 - Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu:
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. 988-1000 - Mohamed I. Ibrahim, Christopher Foy, Dirk R. Englund, Ruonan Han:
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers. 1001-1014
Volume 56, Number 4, April 2021
- Brian P. Ginsburg, Yusuke Oike:
Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits. 1019-1021 - Hyeongseok Seo, Heesun Yoon, Dongkyu Kim, Jungwoo Kim, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi:
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter. 1022-1035 - Matheus F. Pimenta, Çagri Gürleyük, Paul Walsh, Daniel O'Keeffe, Masoud Babaie, Kofi A. A. Makinwa:
A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors. 1036-1045 - Jiannan Huang, Patrick P. Mercier:
A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation. 1046-1057 - Rishika Agarwala, Peng Wang, Henry L. Bishop, Anjana Dissanayake, Benton H. Calhoun:
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. 1058-1070 - Hyochan An, Sam Schiferl, Siddharth Venkatesan, Tim Wesley, Qirui Zhang, Jingcheng Wang, Kyojin Choo, Shiyu Liu, Bowen Liu, Ziyun Li, Luyao Gong, Hengfei Zhong, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim, Dennis Sylvester:
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. 1071-1081 - Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy:
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. 1082-1092 - Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, Jaehoon Heo, Joo-Young Kim:
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. 1093-1104 - Ziyun Li, Zhehong Wang, Li Xu, Qing Dong, Bowen Liu, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw:
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. 1105-1115 - Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. 1116-1128 - Dae-Hoon Na, Jang-Woo Lee, Seon-Kyoo Lee, Hwasuk Cho, Junha Lee, Manjae Yang, Eunjin Song, Anil Kavala, Tongsung Kim, Dong-Su Jang, Youngmin Jo, Ji-Yeon Shin, Byung-Kwan Chun, Tae-Sung Lee, Byunghoon Jeong, Chiweon Yoon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae-Seok Byeon, Jinyub Lee, Jai Hyuk Song:
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. 1129-1140 - Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew:
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. 1141-1151 - Christopher L. Ayala, Tomoyuki Tanaka, Ro Saito, Mai Nozoe, Naoki Takeuchi, Nobuyuki Yoshikawa:
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices. 1152-1165 - Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. 1166-1175