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ORCIDVijay Sundararajan
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2010 – 2019
- 2016
[r2]Vijay Sundararajan:
Gate Sizing. Encyclopedia of Algorithms 2016: 811-814
2000 – 2009
- 2008
- [c14]Vikram Chandrasekhar, Zukang Shen, Vijay Sundararajan:
Optimal power allocation for sum capacity of a slotted three-cell system. ICASSP 2008: 3161-3164 - [r1]Vijay Sundararajan:
Gate Sizing. Encyclopedia of Algorithms 2008 - 2004
- [j4]Vijay Sundararajan, Sachin S. Sapatnekar
, Keshab K. Parhi:
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004) - 2003
- [j3]Vijay Sundararajan, Keshab K. Parhi:
Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems. IEEE Trans. Signal Process. 51(7): 1954-1965 (2003) - 2002
- [j2]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 568-581 (2002) - 2001
- [j1]Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi:
Vector processing of wavelet coefficients for robust image denoising. Image Vis. Comput. 19(7): 435-450 (2001) - [c13]Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi:
Energy efficient signaling in DSM CMOS technology. ISCAS (5) 2001: 411-414 - [c12]Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi:
Energy Efficient Signaling in Deep Submicron CMOS Technology. ISQED 2001: 319-324 - 2000
- [c11]Vijay Sundararajan, Keshab K. Parhi:
Synthesis of low power folded programmable coefficient FIR digital filters (short paper). ASP-DAC 2000: 153-156 - [c10]Vijay Sundararajan, Keshab K. Parhi:
Data transmission over a bus with peak-limited transition activity. ASP-DAC 2000: 221-224 - [c9]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664 - [c8]Vijay Sundararajan, Keshab K. Parhi:
Reducing bus transition activity by limited weight coding with codeword slimming. ACM Great Lakes Symposium on VLSI 2000: 13-16 - [c7]Vijay Sundararajan, Keshab K. Parhi:
A novel multiply multiple accumulator component for low power PDSP design. ICASSP 2000: 3247-3250
1990 – 1999
- 1999
- [c6]Vijay Sundararajan, Keshab K. Parhi:
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. ARVLSI 1999: 170-185 - [c5]Vijay Sundararajan, Keshab K. Parhi:
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. DAC 1999: 72-75 - [c4]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6 - [c3]Vijay Sundararajan, Keshab K. Parhi:
Low power synthesis of dual threshold voltage CMOS VLSI circuits. ISLPED 1999: 139-144 - 1998
- [c2]Vijay Sundararajan, Keshab K. Parhi:
Synthesis of folded, pipelined architectures for multi-dimensional multirate systems. ICASSP 1998: 3089-3092 - 1997
- [c1]Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi:
A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers. ICIP (1) 1997: 632-635
Coauthor Index
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