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"A fast global gate collapsing technique for high performance designs using ..."

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji (1998)

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DOI: 10.1109/ICCD.1998.727062

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/iccd/JiangSB98
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD 1998: 276-281

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