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ORCIDPaul G. Villarrubia
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2010 – 2019
- 2011
[c23]Michael D. Moffitt, Mátyás A. Sustik, Paul G. Villarrubia:
Robust partitioning for hardware-accelerated functional verification. DAC 2011: 854-859
2000 – 2009
- 2008
- [c22]Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong:
Challenges at 45nm and beyond. ICCAD 2008: 7 - [c21]Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment. ISPD 2008: 71-77 - [r1]Gi-Joon Nam, Paul G. Villarrubia:
Placement. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j7]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam
, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j6]Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam:
Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2158-2172 (2007) - [c20]Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 - [c19]Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558 - [c18]Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 - [c17]Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia:
The coming of age of physical synthesis. ICCAD 2007: 246-249 - [c16]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - [p1]Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia:
ISPD 2005/2006 Placement Benchmarks. Modern Circuit Placement 2007: 3-12 - 2006
- [j5]Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia:
On whitespace and stability in physical synthesis. Integr. 39(4): 340-362 (2006) - [j4]Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 678-691 (2006) - 2005
- [c15]Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia:
Diffusion-based placement migration. DAC 2005: 515-520 - [c14]Paul Villarrubia:
Physical design tools for hierarchy. ISPD 2005: 184 - [c13]Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 - [c12]Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz:
The ISPD2005 placement contest and benchmark suite. ISPD 2005: 216-220 - 2004
- [j3]Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden:
Benchmarking for large-scale placement and beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 472-487 (2004) - [c11]Haoxing Ren, David Zhigang Pan, Paul Villarrubia:
True crosstalk aware incremental placement with noise map. ICCAD 2004: 402-409 - 2003
- [j2]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 573-583 (2003) - [j1]Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1343-1353 (2003) - [c10]Saurabh N. Adya, Igor L. Markov, Paul Villarrubia:
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. ICCAD 2003: 311-319 - [c9]Paul Villarrubia:
Important placement considerations for modern VLSI chips. ISPD 2003: 6 - [c8]Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden:
Benchmarking for large-scale placement and beyond. ISPD 2003: 95-103 - 2002
- [c7]Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia:
Free space management for cut-based placement. ICCAD 2002: 746-751 - 2001
- [c6]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 - [c5]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - 2000
- [c4]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717 - [c3]Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty:
Transformational Placement and Synthesis. DATE 2000: 194-201
1990 – 1999
- 1997
- [c2]Shervin Hojat, Paul Villarrubia:
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. ICCD 1997: 206-210
1980 – 1989
- 1989
- [c1]Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel:
IBM RISC chip design methodology. ICCD 1989: 143-147
Coauthor Index
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