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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 1
Volume 1, August 2008
- Hidetoshi Onodera:
Welcome to TSLDM - A New Open-Access Online Journal from IPSJ. 1 - Sudeep Pasricha, Nikil D. Dutt
:
Trends in Emerging On-Chip Interconnect Technologies. 2-17 - Sachin S. Sapatnekar:
Variability and Statistical Design. 18-32 - Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada:
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. 33-47 - Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services. 48-57 - Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi:
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools. 58-66 - Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura:
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition. 67-77 - Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. 78-90 - Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. 91-103 - Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. 104-115 - Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. 116-125 - Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. 126-130
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