Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A Convex Optimization Approach to Transistor Sizing for CMOS Circuits."

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya (1991)

> Home

Details and statistics

DOI: 10.1109/ICCAD.1991.185310

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/iccad/SapatnekarRV91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccad/SapatnekarRV91
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya:
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.