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ORCIDAlex Orailoglu
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- affiliation: University of California, San Diego, USA
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2020 – today
- 2024
[j76]Alex Orailoglu, Marc Reichenbach, Matthias Jung:
Special Issue on SAMOS 2022. Int. J. Parallel Program. 52(1-2): 1-2 (2024)- [c205]Pushpak Raj Gautam, Alex Orailoglu:
Transcoders: A Better Alternative To Denoising Autoencoders. ETS 2024: 1-4 - 2023
- [j75]Elbruz Ozen
, Alex Orailoglu:
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation. IEEE Des. Test 40(2): 59-66 (2023) - [j74]Leon Li, Alex Orailoglu:
Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1044-1057 (2023) - [j73]Elbruz Ozen, Alex Orailoglu:
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1147-1160 (2023) - [c204]Leon Li, Alex Orailoglu:
ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box. ATS 2023: 1-6 - [c203]Leon Li, Alex Orailoglu:
Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation. VTS 2023: 1-6 - 2022
- [j72]Marc Reichenbach, Matthias Jung, Alex Orailoglu:
Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020). Int. J. Parallel Program. 50(2): 187-188 (2022) - [j71]Elbruz Ozen, Alex Orailoglu:
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3934-3945 (2022) - [c202]Leon Li, Alex Orailoglu:
JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption. DATE 2022: 1323-1328 - [e9]Alex Orailoglu, Matthias Jung, Marc Reichenbach:
Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings. Lecture Notes in Computer Science 13227, Springer 2022, ISBN 978-3-031-04579-0 [contents] - [e8]Alex Orailoglu, Marc Reichenbach, Matthias Jung:
Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings. Lecture Notes in Computer Science 13511, Springer 2022, ISBN 978-3-031-15073-9 [contents] - 2021
- [j70]Elbruz Ozen, Alex Orailoglu:
SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 20(5s): 76:1-76:25 (2021) - [j69]Chris Nigh, Alex Orailoglu:
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 544-557 (2021) - [c201]Leon Li, Shuyi Ni, Alex Orailoglu:
JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis. HOST 2021: 292-303 - [c200]Elbruz Ozen, Alex Orailoglu:
Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs. ICCAD 2021: 1-8 - 2020
- [j68]Elbruz Ozen, Alex Orailoglu:
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums. J. Electron. Test. 36(6): 703-718 (2020) - [j67]Elbruz Ozen, Alex Orailoglu:
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3250-3262 (2020) - [c199]Elbruz Ozen, Alex Orailoglu:
Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions. ASP-DAC 2020: 169-174 - [c198]Nickolai Verchok, Alex Orailoglu:
Hunting Sybils in Participatory Mobile Consensus-Based Networks. AsiaCCS 2020: 732-743 - [c197]Chris Nigh, Alex Orailoglu:
Test Pattern Superposition to Detect Hardware Trojans. DATE 2020: 25-30 - [c196]Chengmo Yang, Patrick Cronin, Agamyrat Agambayev, Sule Ozev, A. Enis Çetin, Alex Orailoglu:
A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration. ICCAD 2020: 8:1-8:9 - [c195]Elbruz Ozen, Alex Orailoglu:
Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression. ICCAD 2020: 75:1-75:9 - [c194]Elbruz Ozen, Alex Orailoglu:
Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks. ECML/PKDD (2) 2020: 52-68 - [c193]Chris Nigh, Alex Orailoglu:
Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns. VTS 2020: 1-6 - [e7]Alex Orailoglu, Matthias Jung, Marc Reichenbach:
Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings. Lecture Notes in Computer Science 12471, Springer 2020, ISBN 978-3-030-60938-2 [contents] - [i2]Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020)
2010 – 2019
- 2019
- [j66]Diaa Badawi, Tuba Ayhan, Sule Ozev, Chengmo Yang, Alex Orailoglu, Ahmet Enis Çetin:
Detecting Gas Vapor Leaks Using Uncalibrated Sensors. IEEE Access 7: 155701-155710 (2019) - [c192]Elbruz Ozen, Alex Orailoglu:
The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures. ARCS 2019: 253-266 - [c191]Elbruz Ozen, Alex Orailoglu:
Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications. ATS 2019: 7-12 - [c190]Leon Li, Alex Orailoglu:
Piercing Logic Locking Keys through Redundancy Identification. DATE 2019: 540-545 - [c189]Diaa Badawi, Sule Ozev, Jennifer Blain Christen, Chengmo Yang, Alex Orailoglu, A. Enis Çetin:
Detecting Gas Vapor Leaks through Uncalibrated Sensor Based CPS. ICASSP 2019: 8296-8300 - [c188]Leon Li, Alex Orailoglu:
Shielding Logic Locking from Redundancy Attacks. VTS 2019: 1-6 - [i1]Diaa Badawi, Tuba Ayhan, Sule Ozev, Chengmo Yang, Alex Orailoglu, A. Enis Çetin:
Detecting Gas Vapor Leaks Using Uncalibrated Sensors. CoRR abs/1908.07619 (2019) - 2018
- [c187]Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Variation-Aware Hardware Trojan Detection through Power Side-channel. ITC 2018: 1-10 - 2017
- [c186]Joshua Marxen, Alex Orailoglu:
Ensuring system security through proximity based authentication. ASP-DAC 2017: 330-335 - [c185]Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS 2017: 52-57 - [c184]Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu:
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. ETS 2017: 1-6 - 2016
- [j65]Baris Arslan, Alex Orailoglu:
Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 141-154 (2016) - [j64]Baris Arslan, Alex Orailoglu:
Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2093-2103 (2016) - 2015
- [j63]Mengying Zhao, Alex Orailoglu, Chun Jason Xue:
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1640-1650 (2015) - [c183]Garo Bournoutian, Alex Orailoglu:
Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power. ARCS 2015: 83-95 - [c182]Garo Bournoutian, Alex Orailoglu:
Mobile ecosystem driven application-specific low-power control microarchitecture. ICCD 2015: 720-727 - [e6]Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis:
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 461, Springer 2015, ISBN 978-3-319-23798-5 [contents] - 2014
- [j62]Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu:
Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems. ACM Trans. Embed. Comput. Syst. 13(5s): 156:1-156:24 (2014) - [j61]Mingjing Chen, Alex Orailoglu:
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 734-746 (2014) - [c181]Garo Bournoutian, Alex Orailoglu:
On-device objective-C application optimization framework for high-performance mobile processors. DATE 2014: 1-6 - [c180]Chenchen Fu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu:
Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory. ISLPED 2014: 75-80 - 2013
- [j60]Garo Bournoutian, Alex Orailoglu:
Application-aware adaptive cache architecture for power-sensitive mobile processors. ACM Trans. Embed. Comput. Syst. 13(3): 41:1-41:26 (2013) - [j59]Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li:
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers. ACM Trans. Embed. Comput. Syst. 13(3): 50:1-50:26 (2013) - [c179]Baris Arslan, Alex Orailoglu:
Full exploitation of process variation space for continuous delivery of optimal delay test quality. ASP-DAC 2013: 552-557 - [c178]Mengying Zhao, Alex Orailoglu, Chun Jason Xue:
Profit maximization through process variation aware high level synthesis with speed binning. DATE 2013: 176-181 - [c177]Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu:
Branch Prediction directed Dynamic instruction Cache Locking for embedded systems. RTCSA 2013: 209-216 - [c176]Baris Arslan, Alex Orailoglu:
Tracing the best test mix through multi-variate quality tracking. VTS 2013: 1-6 - [c175]Raymond Paseman, Alex Orailoglu:
Towards a cost-effective hardware trojan detection methodology. VTS 2013: 1-3 - [e5]Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag:
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. IEEE 2013, ISBN 978-1-4799-0522-5 [contents] - 2012
- [j58]Chengmo Yang, Alex Orailoglu:
Tackling Resource Variations Through Adaptive Multicore Execution Frameworks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 132-145 (2012) - [j57]Mingjing Chen, Alex Orailoglu:
On Diagnosis of Timing Failures in Scan Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1102-1115 (2012) - [j56]Mingjing Chen, Alex Orailoglu:
Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2170-2183 (2012) - [c174]Garo Bournoutian, Alex Orailoglu:
Dynamic transient fault detection and recovery for embedded processor datapaths. CODES+ISSS 2012: 43-52 - [c173]Baris Arslan, Alex Orailoglu:
Delay test resource allocation and scheduling for multiple frequency domains. VTS 2012: 114-119 - [c172]Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu:
Small-delay defects detection under process variation using Inter-Path Correlation. VTS 2012: 127-132 - 2011
- [j55]Wenjing Rao, Chengmo Yang, Ramesh Karri, Alex Orailoglu:
Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge. Computer 44(2): 46-53 (2011) - [j54]Yuping Zhang, Chun Jason Xue, Chengmo Yang, Alex Orailoglu:
Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability. J. Parallel Distributed Comput. 71(10): 1400-1410 (2011) - [j53]Chengmo Yang, Alex Orailoglu:
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1996-2009 (2011) - [c171]Baris Arslan, Alex Orailoglu:
Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost. Asian Test Symposium 2011: 323-328 - [c170]Garo Bournoutian, Alex Orailoglu:
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors. CODES+ISSS 2011: 89-98 - [c169]Mingjing Chen, Alex Orailoglu:
Diagnosing scan clock delay faults through statistical timing pruning. DAC 2011: 423-428 - [c168]Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li:
Register allocation for simultaneous reduction of energy and peak temperature on registers. DATE 2011: 20-25 - [c167]Mingjing Chen, Alex Orailoglu:
Diagnosing scan chain timing faults through statistical feature analysis of scan images. DATE 2011: 185-190 - [c166]Chengmo Yang, Alex Orailoglu:
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity. DATE 2011: 1255-1260 - [c165]Baris Arslan, Alex Orailoglu:
Adaptive test optimization through real time learning of test effectiveness. DATE 2011: 1430-1435 - 2010
- [j52]Chengmo Yang, Mingjing Chen, Alex Orailoglu:
Squashing code size in microcoded IPs while delivering high decompression speed. Des. Autom. Embed. Syst. 14(3): 265-284 (2010) - [j51]Garo Bournoutian, Alex Orailoglu:
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. Des. Autom. Embed. Syst. 14(3): 309-326 (2010) - [j50]Sunghoon Chun, Alex Orailoglu:
DiSC: A New Diagnosis Method for Multiple Scan Chain Failures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 2051-2055 (2010) - [c164]Garo Bournoutian, Alex Orailoglu:
Dynamic, non-linear cache architecture for power-sensitive mobile processors. CODES+ISSS 2010: 187-194 - [c163]Kwangyoon Lee, Alex Orailoglu:
High durability in NAND flash memory through effective page reuse mechanisms. CODES+ISSS 2010: 205-212 - [c162]Mingjing Chen, Alex Orailoglu:
Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. DATE 2010: 63-68 - [c161]Raid Ayoub, Alex Orailoglu:
Performance and energy efficient cache migrationapproach for thermal management in embedded systems. ACM Great Lakes Symposium on VLSI 2010: 365-368 - [c160]Baris Arslan, Alex Orailoglu:
Delay test quality maximization through process-aware selection of test set size. ICCD 2010: 390-395 - [c159]Chengmo Yang, Alex Orailoglu:
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations. VLSI-SoC 2010: 396-401 - [c158]Chengmo Yang, Chun Jason Xue, Alex Orailoglu:
Fine-grained adaptive CMP cache sharing through access history exploitation. VLSI-SoC 2010: 420-425 - [c157]Mingjing Chen, Alex Orailoglu:
VDDmin test optimization for overscreening minimization through adaptive scan chain masking. VTS 2010: 313-318 - [e4]João Antonio Martino, Guido Araujo, Alex Orailoglu, Felipe Klein:
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010. ACM 2010, ISBN 978-1-4503-0152-7 [contents]
2000 – 2009
- 2009
- [j49]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Logic Mapping in Crossbar-Based Nanoarchitectures. IEEE Des. Test Comput. 26(1): 68-77 (2009) - [j48]Ozgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu:
Scan Cell Positioning for Boosting the Compression of Fan-Out Networks. J. Comput. Sci. Technol. 24(5): 939-948 (2009) - [j47]Dong Xiang, Dianwei Hu, Qiang Xu, Alex Orailoglu:
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1101-1105 (2009) - [j46]Alex Orailoglu, Laura Pozzi:
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1786-1787 (2009) - [c156]Raid Ayoub, Alex Orailoglu:
Filtering Global History: Power and Performance Efficient Branch Predictor. ASAP 2009: 203-206 - [c155]Garo Bournoutian, Alex Orailoglu:
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. CASES 2009: 117-126 - [c154]Chengmo Yang, Mingjing Chen, Alex Orailoglu:
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. CODES+ISSS 2009: 249-256 - [c153]Chengmo Yang, Alex Orailoglu:
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. DATE 2009: 63-68 - [c152]Saturnino Garcia, Alex Orailoglu:
Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy. DATE 2009: 898-901 - [c151]Mingjing Chen, Alex Orailoglu:
Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience. DFT 2009: 49-57 - [c150]Chengmo Yang, Alex Orailoglu:
Processor reliability enhancement through compiler-directed register file peak temperature reduction. DSN 2009: 468-477 - [c149]Mingjing Chen, Alex Orailoglu:
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation. ACM Great Lakes Symposium on VLSI 2009: 369-374 - [c148]Mingjing Chen, Alex Orailoglu:
Scan power reduction in linear test data compression scheme. ICCAD 2009: 78-82 - 2008
- [j45]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. 91-D(3): 736-746 (2008) - [c147]Chengmo Yang, Alex Orailoglu:
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization. CASES 2008: 11-20 - [c146]Kwangyoon Lee, Alex Orailoglu:
Application specific non-volatile primary memory for embedded systems. CODES+ISSS 2008: 31-36 - [c145]Garo Bournoutian, Alex Orailoglu:
Miss reduction in embedded processors through dynamic, power-friendly cache design. DAC 2008: 304-309 - [c144]Wenjing Rao, Alex Orailoglu:
Towards fault tolerant parallel prefix adders in nanoelectronic systems. DATE 2008: 360-365 - [c143]Mingjing Chen, Alex Orailoglu:
Test cost minimization through adaptive test development. ICCD 2008: 234-239 - [c142]Saturnino Garcia, Alex Orailoglu:
Online test and fault-tolerance for nanoelectronic programmable logic arrays. NANOARCH 2008: 8-15 - [c141]Wenjing Rao, Alex Orailoglu, Keith Marzullo:
Locality aware redundancy allocation in nanoelectronic systems. NANOARCH 2008: 24-31 - [c140]Kwangyoon Lee, Alex Orailoglu:
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. SASP 2008: 69-74 - 2007
- [j44]R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond. Computer 40(1): 25-33 (2007) - [j43]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Towards Nanoelectronics Processor Architectures. J. Electron. Test. 23(2-3): 235-254 (2007) - [j42]Peter Petrov, Alex Orailoglu:
Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. Int. J. Parallel Program. 35(2): 157-177 (2007) - [j41]Yiorgos Makris, Alex Orailoglu:
On the identification of modular test requirements for low cost hierarchical test path construction. Integr. 40(3): 315-325 (2007) - [j40]Clifford Lau, Alex Orailoglu, Kaushik Roy:
Guest Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2342-2344 (2007) - [c139]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725 - [c138]Mingjing Chen, Alex Orailoglu:
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements. ATS 2007: 307-312 - [c137]Chengmo Yang, Alex Orailoglu:
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. CASES 2007: 150-154 - [c136]Chengmo Yang, Alex Orailoglu:
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. CODES+ISSS 2007: 15-20 - [c135]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. DATE 2007: 865-869 - [c134]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. DSN 2007: 216-224 - [c133]Raid Ayoub, Alex Orailoglu:
Power efficient register file update approach for embedded processors. ICCD 2007: 431-437 - [c132]Mingjing Chen, Alex Orailoglu:
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. ICCD 2007: 526-532 - [c131]Kyosun Kim, Ramesh Karri, Alex Orailoglu:
Design automation for hybrid CMOS-nonoelectronics crossbars. NANOARCH 2007: 27-32 - 2006
- [c130]Chengmo Yang, Alex Orailoglu:
Power-efficient instruction delivery through trace reuse. PACT 2006: 192-201 - [c129]Chengmo Yang, Alex Orailoglu:
Power efficient branch prediction through early identification of branch addresses. CASES 2006: 169-178 - [c128]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Topology aware mapping of logic functions onto nanowire-based crossbar architectures. DAC 2006: 723-726 - [c127]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. ETS 2006: 63-68 - [c126]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006: 230-236 - [c125]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. VTS 2006: 214-221 - [c124]Mingjing Chen, Hosam Haggag, Alex Orailoglu:
Decision Tree Based Mismatch Diagnosis in Analog Circuits. VTS 2006: 278-285 - 2005
- [j39]Ozgur Sinanoglu, Alex Orailoglu:
Efficient RT-Level Fault Diagnosis. J. Comput. Sci. Technol. 20(2): 166-174 (2005) - [j38]Ismet Bayraktaroglu, Alex Orailoglu:
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. IEEE Trans. Computers 54(1): 61-75 (2005) - [j37]Peter Petrov, Alex Orailoglu:
A reprogrammable customization framework for efficient branch resolution in embedded processors. ACM Trans. Embed. Comput. Syst. 4(2): 452-468 (2005) - [j36]Ozgur Sinanoglu, Alex Orailoglu:
Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Trans. Reliab. 54(2): 215-223 (2005) - [c123]Rasit Onur Topaloglu, Alex Orailoglu:
Forward discrete probability propagation method for device performance characterization under process variations. ASP-DAC 2005: 220-223 - [c122]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Fault tolerant nanoelectronic processor architectures. ASP-DAC 2005: 311-316 - [c121]Raid Ayoub, Alex Orailoglu:
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. ASP-DAC 2005: 729-734 - [c120]Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu:
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195 - [c119]Peter Petrov, Daniel Tracy, Alex Orailoglu:
Energy-effcient physically tagged caches for embedded processors with virtual memory. DAC 2005: 17-22 - [c118]Rasit Onur Topaloglu, Alex Orailoglu:
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. DAC 2005: 851-856 - [c117]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. ICCD 2005: 533-542 - [e3]Carlos Galup-Montoro, Sergio Bampi, Alex Orailoglu:
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005. ACM 2005 [contents] - 2004
- [j35]Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu:
Seamless Test of Digital Components in Mixed-Signal Paths. IEEE Des. Test Comput. 21(1): 44-55 (2004) - [j34]Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu:
Searching for Global Test Costs Optimization in Core-Based Systems. J. Electron. Test. 20(4): 357-373 (2004) - [j33]Ozgur Sinanoglu, Alex Orailoglu:
Fast and energy-frugal deterministic test through efficient compression and compaction techniques. J. Syst. Archit. 50(5): 257-266 (2004) - [j32]Peter Petrov, Alex Orailoglu:
Transforming Binary Code for Low-Power Embedded Processors. IEEE Micro 24(3): 21-33 (2004) - [j31]Peter Petrov, Alex Orailoglu:
Tag compression for low power in dynamically customizable embedded processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1031-1047 (2004) - [j30]Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu:
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. IEEE Trans. Reliab. 53(2): 269-278 (2004) - [j29]Sule Ozev, Alex Orailoglu:
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 756-765 (2004) - [j28]Peter Petrov, Alex Orailoglu:
Low-power instruction bus encoding for embedded processors. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 812-826 (2004) - [c116]Rasit Onur Topaloglu, Alex Orailoglu:
On mismatch in the deep sub-micron era - from physics to circuits. ASP-DAC 2004: 62-67 - [c115]Ozgur Sinanoglu, Alex Orailoglu:
Efficient RT-level fault diagnosis methodology. ASP-DAC 2004: 212-217 - [c114]Ozgur Sinanoglu, Alex Orailoglu:
Scan Power Minimization through Stimulus and Response Transformations. DATE 2004: 404-409 - [c113]Baris Arslan, Alex Orailoglu:
CircularScan: A Scan Architecture for Test Cost Reduction. DATE 2004: 1290-1295 - [c112]Ozgur Sinanoglu, Alex Orailoglu:
Pipelined test of SOC cores through test data transformations. ETS 2004: 86-91 - [c111]Wenjing Rao, Alex Orailoglu, George Su:
Frugal linear network-based test decompression for drastic test cost reductions. ICCAD 2004: 721-725 - [c110]Baris Arslan, Alex Orailoglu:
Design space exploration for aggressive test cost reduction in CircularScan architectures. ICCAD 2004: 726-731 - [c109]Sule Ozev, Alex Orailoglu:
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. ICCD 2004: 72-77 - [c108]Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs. ICCD 2004: 200-203 - [c107]Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. ITC 2004: 472-478 - [c106]Baris Arslan, Alex Orailoglu:
Test Cost Reduction Through A Reconfigurable Scan Architecture. ITC 2004: 945-952 - [c105]Ozgur Sinanoglu, Alex Orailoglu:
Autonomous Yet Deterministic Test of SOC Cores. ITC 2004: 1359-1368 - [c104]Raid Ayoub, Peter Petrov, Alex Orailoglu:
Application specific instruction memory transformations for power efficient, fault resilient embedded processors. SoCC 2004: 195-198 - [e2]Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch:
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004. ACM 2004, ISBN 1-58113-937-3 [contents] - 2003
- [j27]Alex Orailoglu, Alexander V. Veidenbaum:
Guest Editors' Introduction: Application-Specific Microprocessors. IEEE Des. Test Comput. 20(1): 6-7 (2003) - [j26]Peter Petrov, Alex Orailoglu:
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. IEEE Des. Test Comput. 20(1): 18-25 (2003) - [j25]Ozgur Sinanoglu, Alex Orailoglu:
Compacting Test Responses for Deeply Embedded SoC Cores. IEEE Des. Test Comput. 20(4): 22-30 (2003) - [j24]Sule Ozev, Alex Orailoglu:
Statistical Tolerance Analysis for Assured Analog Test Coverage. J. Electron. Test. 19(2): 173-182 (2003) - [j23]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electron. Test. 19(4): 457-467 (2003) - [j22]Alex Orailoglu:
Guest Editor's Introduction. Int. J. Parallel Program. 31(6): 407-409 (2003) - [j21]Ismet Bayraktaroglu, Alex Orailoglu:
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. IEEE Trans. Computers 52(11): 1480-1489 (2003) - [c103]Ozgur Sinanoglu, Alex Orailoglu:
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. Asian Test Symposium 2003: 202-209 - [c102]Baris Arslan, Alex Orailoglu:
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. Asian Test Symposium 2003: 230-235 - [c101]Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu:
Test application time and volume compression through seed overlapping. DAC 2003: 732-737 - [c100]Peter Petrov, Alex Orailoglu:
Power Efficiency through Application-Specific Instruction Memory Transformations. DATE 2003: 10030-10035 - [c99]Wenjing Rao, Alex Orailoglu:
Virtual Compression through Test Vector Stitching for Scan Based Designs. DATE 2003: 10104-10109 - [c98]Peter Petrov, Alex Orailoglu:
Low-power Branch Target Buffer for Application-Specific Embedded Processors. DSD 2003: 158-165 - [c97]Ozgur Sinanoglu, Alex Orailoglu:
Hierarchical Constraint Conscious RT-level Test Generation. DSD 2003: 312-318 - [c96]Peter Petrov, Alex Orailoglu:
Customizable Embedded Processor Architectures. DSD 2003: 468-475 - [c95]Ozgur Sinanoglu, Alex Orailoglu:
Parity-based output compaction for core-based SOCs [logic testing]. ETW 2003: 15-20 - [c94]Ozgur Sinanoglu, Alex Orailoglu:
Partial Core Encryption for Performance-Efficient Test of SOCs. ICCAD 2003: 91-94 - [c93]Peter Petrov, Alex Orailoglu:
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. ICCAD 2003: 523-528 - [c92]Peter Petrov, Alex Orailoglu:
Virtual Page Tag Reduction for Low-power TLBs. ICCD 2003: 371-374 - [c91]Ozgur Sinanoglu, Alex Orailoglu:
Aggressive Test Power Reduction Through Test Stimuli Transformation. ICCD 2003: 542-547 - [c90]Ozgur Sinanoglu, Alex Orailoglu:
Modeling Scan Chain Modifications For Scan-in Test Power Minimization. ITC 2003: 602-611 - [c89]Ismet Bayraktaroglu, Alex Orailoglu:
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. VTS 2003: 113-120 - [e1]Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou:
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003. ACM 2003, ISBN 1-58113-742-7 [contents] - 2002
- [j20]Ismet Bayraktaroglu, Alex Orailoglu:
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. IEEE Des. Test Comput. 19(1): 42-53 (2002) - [j19]Sule Ozev, Christian Olgaard, Alex Orailoglu:
Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. IEEE Des. Test Comput. 19(5): 82-91 (2002) - [j18]Yiorgos Makris, Jamison Collins, Alex Orailoglu:
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. J. Electron. Test. 18(1): 29-42 (2002) - [j17]Ozgur Sinanoglu, Alex Orailoglu:
Efficient Construction of Aliasing-Free Compaction Circuitry. IEEE Micro 22(5): 82-92 (2002) - [j16]Laurence Goodby, Alex Orailoglu, Paul M. Chau:
Microarchitectural synthesis of performance-constrained, low-power VLSI designs. ACM Trans. Design Autom. Electr. Syst. 7(1): 122-136 (2002) - [c88]Yiorgos Makris, Alex Orailoglu:
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. Asian Test Symposium 2002: 134-139 - [c87]Peter Petrov, Alex Orailoglu:
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. CODES 2002: 181-186 - [c86]Ismet Bayraktaroglu, Alex Orailoglu:
Gate Level Fault Diagnosis in Scan-Based BIST. DATE 2002: 376-381 - [c85]Sherief Reda, Alex Orailoglu:
Reducing Test Application Time Through Test Data Mutation Encoding. DATE 2002: 387-393 - [c84]Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu:
Test Planning and Design Space Exploration in a Core-Based Environment. DATE 2002: 478-485 - [c83]Peter Petrov, Alex Orailoglu:
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. DATE 2002: 1065-1071 - [c82]Ozgur Sinanoglu, Alex Orailoglu:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. DFT 2002: 325-333 - [c81]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Dynamic test data transformations for average and peak power reductions. ETW 2002: 113-118 - [c80]Ozgur Sinanoglu, Alex Orailoglu:
A novel scan architecture for power-efficient, rapid test. ICCAD 2002: 299-303 - [c79]Sule Ozev, Alex Orailoglu:
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. ICCD 2002: 258-264 - [c78]Baris Arslan, Alex Orailoglu:
Fault Dictionary Size Reduction through Test Response Superposition. ICCD 2002: 480- - [c77]Sule Ozev, Alex Orailoglu, Hosam Haggag:
Automated test development and test time reduction for RF subsystems. ISCAS (1) 2002: 581-584 - [c76]Sule Ozev, Alex Orailoglu:
An Integrated Tool for Analog Test Generation and Fault Simulation. ISQED 2002: 267-272 - [c75]Sherief Reda, Rolf Drechsler, Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399 - [c74]Alex Orailoglu, Peter Petrov:
Low-Power Data Memory Communication for Application-Specific Embedded Processors. ISSS 2002: 219-224 - [c73]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC 2002: 844-850 - [c72]Érika F. Cota, Luigi Carro, Alex Orailoglu, Marcelo Lubaszewski:
Generic and Detailed Search for TAM Definition in Core-Based Systems. LATW 2002: 160-164 - [c71]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions. VTS 2002: 166-172 - [c70]Sule Ozev, Alex Orailoglu:
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. VTS 2002: 213-222 - 2001
- [j15]Ismet Bayraktaroglu, Alex Orailoglu:
Concurrent test for digital linear systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1132-1142 (2001) - [j14]Peter Petrov, Alex Orailoglu:
Performance and power effectiveness in embedded processors customizable partitioned caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1309-1318 (2001) - [c69]Ozgur Sinanoglu, Alex Orailoglu:
Compaction Schemes with Minimum Test Application Time. Asian Test Symposium 2001: 199-204 - [c68]Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu:
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. Asian Test Symposium 2001: 319-324 - [c67]Ismet Bayraktaroglu, Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? Asian Test Symposium 2001: 373-378 - [c66]Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu:
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems. CICC 2001: 263-266 - [c65]Peter Petrov, Alex Orailoglu:
Towards effective embedded processors in codesigns: customizable partitioned caches. CODES 2001: 79-84 - [c64]Ismet Bayraktaroglu, Alex Orailoglu:
Test Volume and Application Time Reduction Through Scan Chain Concealment. DAC 2001: 151-155 - [c63]Peter Petrov, Alex Orailoglu:
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. DAC 2001: 512-517 - [c62]Ismet Bayraktaroglu, Alex Orailoglu:
Diagnosis for scan-based BIST: reaching deep into the signatures. DATE 2001: 102-111 - [c61]Peter Petrov, Alex Orailoglu:
Data cache energy minimizations through programmable tag size matching to the applications. ISSS 2001: 113-117 - [c60]Ozgur Sinanoglu, Alex Orailoglu:
Space and time compaction schemes for embedded cores. ITC 2001: 521-529 - [c59]Christian Olgaard, Sule Ozev, Alex Orailoglu:
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. ITC 2001: 965-974 - [c58]Ismet Bayraktaroglu, Alex Orailoglu:
Improved Methods for Fault Diagnosis in Scan-Based BIST. LATW 2001: 169-172 - [c57]Ozgur Sinanoglu, Alex Orailoglu:
RT-level Fault Simulation Based on Symbolic Propagation. VTS 2001: 240-245 - [c56]Yiorgos Makris, Vishal Patel, Alex Orailoglu:
Efficient Transparency Extraction and Utilization in Hierarchical Test. VTS 2001: 246-251 - 2000
- [j13]Samuel Norman Hamilton, Alex Orailoglu:
On-line test for fault-secure fault identification. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 446-452 (2000) - [c55]Yiorgos Makris, Jamison Collins, Alex Orailoglu:
Fast hierarchical test path construction for DFT-free controller-datapath circuits. Asian Test Symposium 2000: 185-190 - [c54]Ismet Bayraktaroglu, Alex Orailoglu:
Accumulation-based concurrent fault detection for linear digital state variable systems. Asian Test Symposium 2000: 484- - [c53]Yiorgos Makris, Alex Orailoglu, Praveen Vishakantaiah:
Modular test generation and concurrent transparency-based test translation using gate-level ATPG. CICC 2000: 75-78 - [c52]Ismet Bayraktaroglu, Alex Orailoglu:
Improved fault diagnosis in scan-based BIST via superposition. DAC 2000: 55-58 - [c51]Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu:
Test Synthesis for Mixed-Signal SOC Paths. DATE 2000: 128-133 - [c50]Laurence Goodby, Alex Orailoglu:
Test Quality and Fault Risk in Digital Filter Datapath BIST. DATE 2000: 468-475 - [c49]Yiorgos Makris, Jamison Collins, Alex Orailoglu:
How to avoid random walks in hierarchical test path identification. ETW 2000: 111-116 - [c48]Ismet Bayraktaroglu, Alex Orailoglu:
Low cost concurrent test implementation for linear digital systems. ETW 2000: 140-143 - [c47]Ismet Bayraktaroglu, Alex Orailoglu:
Cost effective digital filter design for concurrent test. ICASSP 2000: 3323-3326 - [c46]Yiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah:
Transparency-based hierarchical test generation for modular RTL designs. ISCAS 2000: 689-692 - [c45]Ismet Bayraktaroglu, Alex Orailoglu:
Unifying methodologies for high fault coverage concurrent and off-line test of digital filters. ISCAS 2000: 705-708 - [c44]Ismet Bayraktaroglu, Alex Orailoglu:
Deterministic partitioning techniques for fault diagnosis in scan-based BIST. ITC 2000: 273-282 - [c43]Sule Ozev, Alex Orailoglu:
Block-Based Test Integration for Analog Integrated Circuits. LATW 2000: 128-132 - [c42]Yiorgos Makris, Alex Orailoglu:
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test. LATW 2000: 250-255 - [c41]Sule Ozev, Alex Orailoglu:
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. VTS 2000: 149-156 - [c40]Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu:
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. VTS 2000: 459-464
1990 – 1999
- 1999
- [j12]Laurence Goodby, Alex Orailoglu:
Redundancy and testability in digital filter datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 631-644 (1999) - [c39]Yiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah:
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation. CICC 1999: 159-162 - [c38]Yiorgos Makris, Alex Orailoglu:
Channel-Based Behavioral Test Synthesis for Improved Module Reachability. DATE 1999: 283-288 - [c37]Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig:
Self Recovering Controller and Datapath Codesign. DATE 1999: 596-601 - [c36]Sule Ozev, Alex Orailoglu:
Low-Cost Test for Large Analog IC's. DFT 1999: 101- - [c35]Yiorgos Makris, Alex Orailoglu:
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. DFT 1999: 339-347 - [c34]Yiorgos Makris, Alex Orailoglu:
Property-based testability analysis for hierarchical RTL designs. ICECS 1999: 1089-1092 - [c33]Ismet Bayraktaroglu, Alex Orailoglu:
Low-Cost On-Line Test for Digital Filters. VTS 1999: 446-451 - 1998
- [j11]Samuel Norman Hamilton, Alex Orailoglu:
Efficient Self-Recovering ASIC Design. IEEE Des. Test Comput. 15(4): 25-35 (1998) - [j10]Alex Orailoglu:
On-Line Fault Resilience Through Gracefully Degradable ASICs. J. Electron. Test. 12(1-2): 145-151 (1998) - [j9]Yiorgos Makris, Alex Orailoglu:
RTL Test Justification and Propagation Analysis for Modular Designs. J. Electron. Test. 13(2): 105-120 (1998) - [c32]Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs. Asian Test Symposium 1998: 440- - [c31]Samuel Norman Hamilton, Alex Orailoglu:
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. DATE 1998: 604-609 - [c30]Samuel Norman Hamilton, Alex Orailoglu:
Transient and Intermittent Fault Recovery without Rollback. DFT 1998: 252-260 - [c29]Alex Orailoglu:
Graceful Degradation in Synthesis of VLSI ICs. DFT 1998: 301-311 - [c28]Yiorgos Makris, Alex Orailoglu:
DFT guidance through RTL test justification and propagation analysis. ITC 1998: 668-677 - 1997
- [j8]Alex Orailoglu:
Microarchitectural synthesis for rapid BIST testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 573-586 (1997) - [j7]Ian G. Harris, Alex Orailoglu:
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction. VLSI Design 5(2): 167-182 (1997) - [c27]Laurence Goodby, Alex Orailoglu:
Frequency-Domain Compatibility in Digital Filter BIST. DAC 1997: 540-545 - [c26]Samuel Norman Hamilton, Alex Orailoglu:
Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation. FTCS 1997: 329-338 - 1996
- [j6]Ramesh Karri, Karin Högstedt, Alex Orailoglu:
Computer-Aided Design of Fault-Tolerant VLSI Systems. IEEE Des. Test Comput. 13(3): 88-96 (1996) - [j5]Alex Orailoglu, Ramesh Karri:
Automatic Synthesis of Self-Recovering VLSI Systems. IEEE Trans. Computers 45(2): 131-142 (1996) - [j4]Ramesh Karri, Alex Orailoglu:
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors. IEEE Trans. Reliab. 45(3): 404-412 (1996) - [c25]Laurence Goodby, Alex Orailoglu:
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. DAC 1996: 813-818 - [c24]Wah Chan, Alex Orailoglu:
High-level synthesis of gracefully degradable ASICs. ED&TC 1996: 50-54 - [c23]Laurence Goodby, Alex Orailoglu:
Variance mismatch: identifying random-test resistance in DSP datapaths. ICASSP 1996: 3205-3208 - [c22]Alex Orailoglu:
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. ICCD 1996: 112-117 - [c21]R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu:
Can Defect-Tolerant Chips Better Meet the Quality Challenge? VTS 1996: 362-363 - 1995
- [c20]Mahsa Vahidi, Alex Orailoglu:
Metric-based transformations for self testable VLSI designs with high test concurrency. EURO-DAC 1995: 136-141 - [c19]Laurence Goodby, Alex Orailoglu:
Towards 100% Testable FIR Digital Filters. ITC 1995: 394-402 - [c18]Mahsa Vahidi, Alex Orailoglu:
Testability metrics for synthesis of self-testable designs and effective test plans. VTS 1995: 170-175 - 1994
- [j3]Alex Orailoglu, Ramesh Karri:
Synthesis of fault-tolerant and real-time microarchitectures. J. Syst. Softw. 25(1): 73-84 (1994) - [j2]Alex Orailoglu, Ramesh Karri:
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 304-311 (1994) - [c17]Ian G. Harris, Alex Orailoglu:
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. DAC 1994: 206-211 - [c16]Ramesh Karri, Alex Orailoglu:
Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. DAC 1994: 552-556 - [c15]Ian G. Harris, Alex Orailoglu:
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123 - [c14]Ramesh Karri, Alex Orailoglu:
Simulated annealing based yield enhancement of layouts. Great Lakes Symposium on VLSI 1994: 166-169 - [c13]Ian G. Harris, Alex Orailoglu:
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. ICCD 1994: 101-104 - [c12]Laurence Goodby, Alex Orailoglu, Paul M. Chau:
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. ICCD 1994: 323-326 - [c11]Karin Högstedt, Alex Orailoglu:
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. ICCD 1994: 331-334 - [c10]Ramesh Karri, Karin Högstedt, Alex Orailoglu:
Rapid prototyping of fault-tolerant VLSI systems. HLSS 1994: 126-131 - 1993
- [c9]Ramesh Karri, Alex Orailoglu:
High-Level Synthesis of Fault-Secure Microarchitectures. DAC 1993: 429-433 - [c8]Ramesh Karri, Alex Orailoglu:
Optimal Self-Recovering Microarchitecture Synthesis. FTCS 1993: 512-521 - [c7]Alex Orailoglu, Ian G. Harris:
Test Path Generation and Test Scheduling for Self-Testable Designs. ICCD 1993: 528-531 - [c6]Ian G. Harris, Alex Orailoglu:
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. ISCAS 1993: 1682-1685 - 1992
- [c5]Ramesh Karri, Alex Orailoglu:
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. DAC 1992: 662-665 - [c4]Ramesh Karri, Alex Orailoglu:
Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. FTCS 1992: 519-526 - [c3]Alex Orailoglu, Ramesh Karri:
High-Level Synthesis of Self-Recovering MicroArchitectures. ICCD 1992: 286-289 - 1991
- [j1]Amir K. Hekmatpour, Alex Orailoglu, Paul M. Chau:
Hierarchical Modeling of the VLSI Design Process. IEEE Expert 6(2): 56-70 (1991) - [c2]Ramesh Karri, Alex Orailoglu:
ALPS: An Algorithm for Pipeline Data Path Synthesis. MICRO 1991: 124-132
1980 – 1989
- 1986
- [c1]Alex Orailoglu, Daniel Gajski:
Flow graph representation. DAC 1986: 503-509 - 1983
- [b1]Alex Orailoglu:
Software Design Issues in the Implementation of Hierarchical, Display Editors. University of Illinois Urbana-Champaign, USA, 1983
Coauthor Index
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