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ORCIDJeyavijayan Rajendran
Jeyavijayan (JV) Rajendran – J. V. Rajendran 0001
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- affiliation: Texas A&M University, Kingsville, TX, USA
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2020 – today
- 2023
[c71]Hao Guo, Sayandeep Saha, Vasudev Gohil, Satwik Patnaik, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran:
ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning. DAC 2023: 1-6- [c70]Chen Chen, Rahul Kande, Nathan Nguyen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
HyPFuzz: Formal-Assisted Processor Fuzzing. USENIX Security Symposium 2023: 1361-1378 - [c69]Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran:
FuncTeller: How Well Does eFPGA Hide Functionality? USENIX Security Symposium 2023: 5809-5826 - [i19]Chen Chen, Rahul Kande, Nathan Nyugen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
HyPFuzz: Formal-Assisted Processor Fuzzing. CoRR abs/2304.02485 (2023) - [i18]Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran:
FuncTeller: How Well Does eFPGA Hide Functionality? CoRR abs/2306.05532 (2023) - [i17]Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri
, Jeyavijayan Rajendran:
LLM-assisted Generation of Hardware Assertions. CoRR abs/2306.14027 (2023) - [i16]Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu:
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. CoRR abs/2307.02569 (2023) - [i15]Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. CoRR abs/2307.14480 (2023) - [i14]Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. CoRR abs/2311.14594 (2023) - 2022
- [j27]Srini Devadas, Jeyavijayan Rajendran:
Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. IEEE Des. Test 39(4): 5-6 (2022) - [j26]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Trans. Emerg. Top. Comput. 10(1): 386-403 (2022) - [c68]Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran:
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CCS 2022: 1275-1289 - [c67]Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan (JV) Rajendran:
DETERRENT: detecting trojans using reinforcement learning. DAC 2022: 697-702 - [c66]Chen Chen, Rahul Kande, Pouya Mahmoody, Ahmad-Reza Sadeghi, J. V. Rajendran:
Trusting the trust anchor: towards detecting cross-layer vulnerabilities with hardware fuzzing. DAC 2022: 1379-1383 - [c65]Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava:
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. ICCAD 2022: 25:1-25:8 - [c64]Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan (JV) Rajendran:
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. ISOCC 2022: 217-218 - [c63]Rahul Kande, Addison Crump, Garrett Persyn, Patrick Jauernig, Ahmad-Reza Sadeghi, Aakash Tyagi, Jeyavijayan Rajendran:
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. USENIX Security Symposium 2022: 3219-3236 - [i13]Aakash Tyagi, Addison Crump, Ahmad-Reza Sadeghi, Garrett Persyn, Jeyavijayan Rajendran, Patrick Jauernig, Rahul Kande:
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. CoRR abs/2201.09941 (2022) - [i12]Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan Rajendran:
DETERRENT: Detecting Trojans using Reinforcement Learning. CoRR abs/2208.12878 (2022) - [i11]Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran:
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CoRR abs/2208.12897 (2022) - [i10]Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan Rajendran:
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. CoRR abs/2208.13885 (2022) - [i9]Hao Guo, Sayandeep Saha, Satwik Patnaik, Vasudev Gohil, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran:
Vulnerability Assessment of Ciphers To Fault Attacks Using Reinforcement Learning. IACR Cryptol. ePrint Arch. 2022: 1468 (2022) - 2021
- [j25]Siddharth Garg, Daniel E. Holcomb, Jeyavijayan (JV) Rajendran, Ahmad-Reza Sadeghi:
Guest Editors' Introduction: Competing to Secure SoCs. IEEE Des. Test 38(1): 5-6 (2021) - [j24]Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio:
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 36-41 (2021) - [j23]Vasudev Gohil, Mark Tressler, Kevin Sipple, Satwik Patnaik, Jeyavijayan Rajendran:
Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. IEEE Trans. Inf. Forensics Secur. 16: 5077-5092 (2021) - [c62]Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande:
Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned. ACM Great Lakes Symposium on VLSI 2021: 95-100 - [c61]Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran:
Does logic locking work with EDA tools? USENIX Security Symposium 2021: 1055-1072 - 2020
- [b1]Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Trustworthy Hardware Design: Combinational Logic Locking Techniques. Springer 2020, ISBN 978-3-030-15333-5, pp. 1-137 - [j22]Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak:
Keynote: A Disquisition on Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 1952-1972 (2020) - [j21]Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu, Wujie Wen, Jeyavijayan Rajendran:
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2192-2205 (2020) - [j20]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Trans. Emerg. Top. Comput. 8(2): 517-532 (2020) - [j19]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Breaking Analog Locking Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2157-2170 (2020) - [c60]Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran:
Multi-Objective Strategies for Stripped-Functionality Logic Locking. ISCAS 2020: 1-5 - [c59]Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran:
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. ITC 2020: 1-10 - [i8]Chenglu Jin, Vasudev Gohil, Ramesh Karri, Jeyavijayan Rajendran:
Security of Cloud FPGAs: A Survey. CoRR abs/2005.04867 (2020) - [i7]Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020)
2010 – 2019
- 2019
- [c58]Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu:
Layout recognition attacks on split manufacturing. ASP-DAC 2019: 45-50 - [c57]Muhammad Yasin, Chongzhi Zhao, Jeyavijayan (JV) Rajendran:
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. ICCAD 2019: 1-4 - [c56]Ryan Vrecenar, Michael Hall, Joshua Zshiesche, Mahesh Naidu, Jeyavijayan Rajendran, Stavros Kalafatis:
Red Teaming a Multi-Colored Bluetooth Bulb. ICCD 2019: 293-296 - [c55]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Breaking Analog Locking Techniques via Satisfiability Modulo Theories. ITC 2019: 1-10 - [c54]Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
HardFails: Insights into Software-Exploitable Hardware Bugs. USENIX Security Symposium 2019: 213-230 - [c53]Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan (JV) Rajendran, Naghmeh Karimi:
Special Session: Countering IP Security threats in Supply chain. VTS 2019: 1-9 - 2018
- [j18]Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran:
The Cat and Mouse in Split Manufacturing. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 805-817 (2018) - [c52]Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran:
Towards provably-secure performance locking. DATE 2018: 1592-1597 - [c51]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards provably-secure analog and mixed-signal locking against overproduction. ICCAD 2018: 7 - [c50]Ro Cammarota, Naghmeh Karimi, Siddharth Garg, Jeyavijayan Rajendran:
Special session: Recent developments in hardware security. VTS 2018: 1 - [i6]Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs. CoRR abs/1812.00197 (2018) - [i5]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IACR Cryptol. ePrint Arch. 2018: 1064 (2018) - 2017
- [j17]Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Trans. Inf. Forensics Secur. 12(11): 2668-2682 (2017) - [c49]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Security analysis of Anti-SAT. ASP-DAC 2017: 342-347 - [c48]Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran:
Routing perturbation for enhanced security in split manufacturing. ASP-DAC 2017: 605-510 - [c47]Giovanni Di Crescenzo, Jeyavijayan Rajendran, Ramesh Karri, Nasir D. Memon:
Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization. ASHES@CCS 2017: 7-16 - [c46]Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Provably-Secure Logic Locking: From Theory To Practice. CCS 2017: 1601-1618 - [c45]Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran:
What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI 2017: 351-356 - [c44]Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu:
TTLock: Tenacious and traceless logic locking. HOST 2017: 166 - [c43]Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran:
On designing optimal camouflaged layouts. HOST 2017: 169 - [c42]Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran:
Front-end-of-line attacks in split manufacturing. ICCAD 2017: 1-8 - [c41]Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. ICCAD 2017: 313-320 - [c40]Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. ICCAD 2017: 321-328 - [c39]Jeyavijayan (JV) Rajendran:
An overview of hardware intellectual property protection. ISCAS 2017: 1-4 - [c38]Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani:
DFS covert channels on multi-core platforms. VLSI-SoC 2017: 1-6 - [c37]Jeyavijayan (JV) Rajendran, Peilin Song, Suriya Natarajan:
Innovative practices session 3C hardware security. VTS 2017: 1 - [i4]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Removal Attacks on Logic Locking and Camouflaging Techniques. IACR Cryptol. ePrint Arch. 2017: 348 (2017) - 2016
- [j16]Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, Krishnendu Chakrabarty:
Supply-Chain Security of Digital Microfluidic Biochips. Computer 49(8): 36-43 (2016) - [j15]Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri:
On Improving the Security of Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1411-1424 (2016) - [j14]Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2946-2959 (2016) - [c36]Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran:
The cat and mouse in split manufacturing. DAC 2016: 165:1-165:6 - [c35]Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Activation of logic encrypted chips: Pre-test or post-test? DATE 2016: 139-144 - [c34]Md. Badruddoja Majumder, Mesbah Uddin, Garrett S. Rose, Jeyavijayan Rajendran:
Sneak path enabled authentication for memristive crossbar memories. AsianHOST 2016: 1-6 - [c33]Arun K. Kanuparthi, Jeyavijayan Rajendran, Ramesh Karri:
Controlling your control flow graph. HOST 2016: 43-48 - [c32]Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu:
SARLock: SAT attack resistant logic locking. HOST 2016: 236-241 - [c31]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
CamoPerturb: secure IC camouflaging for minterm protection. ICCAD 2016: 29 - [c30]Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran:
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect. ICCAD 2016: 97 - [c29]Mohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris:
Hardware-based attacks to compromise the cryptographic security of an election system. ICCD 2016: 153-156 - [c28]Jeyavijayan Rajendran, Jack Tang, Ramesh Karri:
Securing pressure measurements using SensorPUFs. ISCAS 2016: 1330-1333 - [c27]Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri:
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. VLSID 2016: 547-552 - [i3]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Security Analysis of Anti-SAT. IACR Cryptol. ePrint Arch. 2016: 896 (2016) - [i2]Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging. IACR Cryptol. ePrint Arch. 2016: 978 (2016) - 2015
- [j13]Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki:
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proc. IEEE 103(5): 829-849 (2015) - [j12]Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Fault Analysis-Based Logic Encryption. IEEE Trans. Computers 64(2): 410-424 (2015) - [j11]Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose:
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Trans. Computers 64(3): 733-746 (2015) - [j10]Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri:
Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1756-1769 (2015) - [c26]Jeyavijayan Rajendran, Vivekananda Vedula, Ramesh Karri:
Detecting malicious modifications of data in third-party intellectual property cores. DAC 2015: 112:1-112:6 - 2014
- [j9]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE 102(8): 1266-1282 (2014) - [j8]Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri:
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. IEEE Trans. Emerg. Top. Comput. 2(4): 461-472 (2014) - [c25]Adam Waksman, Jeyavijayan Rajendran, Matthew Suozzo, Simha Sethumadhavan:
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. DAC 2014: 175:1-175:4 - [c24]Davood Shahrjerdi, Jeyavijayan Rajendran, Siddharth Garg, Farinaz Koushanfar, Ramesh Karri:
Shielding and securing integrated circuits with sensors. ICCAD 2014: 170-174 - [c23]David H. K. Hoe, Jeyavijayan Rajendran, Ramesh Karri:
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. ISVLSI 2014: 516-521 - [c22]Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran:
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS 2014: 1 - 2013
- [j7]Jeyavijayan Rajendran, Arun K. Kanuparthi, Mohamed Zahran, Sateesh Addepalli, Gaston Ormazabal, Ramesh Karri:
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Des. Test 30(2): 35-44 (2013) - [c21]Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki:
Hardware security strategies exploiting nanoelectronic circuits. ASP-DAC 2013: 368-372 - [c20]Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri:
Security analysis of integrated circuit camouflaging. CCS 2013: 709-720 - [c19]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Is split manufacturing secure? DATE 2013: 1259-1264 - [c18]Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri:
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. DFTS 2013: 101-106 - [c17]Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, Yiorgos Makris:
Reconciling the IC test and security dichotomy. ETS 2013: 1-6 - [c16]Masoud Rostami, Farinaz Koushanfar, Jeyavijayan Rajendran, Ramesh Karri:
Hardware security: threat models and metrics. ICCAD 2013: 819-823 - [c15]Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri:
High-level synthesis for security and trust. IOLTS 2013: 232-233 - [c14]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
VLSI testing based security metric for IC camouflaging. ITC 2013: 1-4 - [c13]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Sneak-path Testing of Memristor-based Memories. VLSI Design 2013: 386-391 - [c12]Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri:
A study on the effectiveness of Trojan detection techniques using a red team blue team approach. VTS 2013: 1-3 - 2012
- [j6]Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose:
Design Considerations for Multilevel CMOS/Nano Memristive Memory. ACM J. Emerg. Technol. Comput. Syst. 8(1): 6:1-6:22 (2012) - [j5]Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino:
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proc. IEEE 100(6): 2033-2049 (2012) - [j4]Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Trans. Computers 61(4): 474-487 (2012) - [j3]Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose:
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5): 1051-1060 (2012) - [c11]Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Security analysis of logic obfuscation. DAC 2012: 83-89 - [c10]Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Logic encryption: A fault analysis perspective. DATE 2012: 953-958 - [c9]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Engineering crossbar based emerging memory technologies. ICCD 2012: 478-479 - [c8]Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak:
Nano-PPUF: A Memristor-Based Security Primitive. ISVLSI 2012: 84-87 - [i1]Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki:
Nanoelectronic Solutions for Hardware Security. IACR Cryptol. ePrint Arch. 2012: 575 (2012) - 2011
- [j2]Mohammad Tehranipoor, Hassan Salmani, Xuehui Zhang, Michel Wang, Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld:
Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. Computer 44(7): 66-74 (2011) - [c7]