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Daniel Gajski
Daniel D. Gajski
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- affiliation: University of California, Irvine, USA
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2010 – 2019
- 2016
- [j52]Fadi J. Kurdahi, Mohammad Abdullah Al Faruque, Daniel Gajski, Ahmed M. Eltawil:
A case study to develop a graduate-level degree program in embedded & cyber-physical systems. SIGBED Rev. 14(1): 16-21 (2016) - 2015
- [j51]Wenliang He, Daniel Gajski, George Farkas, Mark Warschauer:
Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds? Comput. Educ. 81: 59-68 (2015) - 2014
- [c167]Kyoungwon Kim, Daniel D. Gajski:
Trace-Driven Performance Estimation of multi-core platforms. MWSCAS 2014: 627-630 - [c166]Kyoungwon Kim, Daniel D. Gajski:
Hierarchy-Aware mapping of pipelined applications. MWSCAS 2014: 631-634 - 2012
- [j50]Jelena Trajkovic
, Samar Abdi, Gabriela Nicolescu, Daniel D. Gajski:
Automated Generation of Custom Processor Core from C Code. J. Electr. Comput. Eng. 2012: 862469:1-862469:26 (2012) - 2011
- [j49]Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner
, Daniel D. Gajski:
Automatic TLM Generation for Early Validation of Multicore Systems. IEEE Des. Test Comput. 28(3): 10-19 (2011) - 2010
- [c165]Daniel Gajski, Todd M. Austin, Steve Svoboda:
What input-language is the best choice for high level synthesis (HLS)? DAC 2010: 857-858 - [c164]Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski:
Accurate timed RTOS model for transaction level modeling. DATE 2010: 1333-1336 - [c163]Ines Viskic, Lochi Yu, Daniel Gajski:
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. LCTES 2010: 77-84 - [c162]Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski:
Embedded system environment: A framework for TLM-based design and prototyping. International Symposium on Rapid System Prototyping 2010: 1-7 - [c161]Jelena Trajkovic
, Daniel D. Gajski:
Early performance-cost estimation of application-specific data path pipelining. SASP 2010: 107-110
2000 – 2009
- 2009
- [j48]Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach:
An Introduction to High-Level Synthesis. IEEE Des. Test Comput. 26(4): 8-17 (2009) - [j47]Samar Abdi, Daniel Gajski, Ines Viskic:
Model Based Synthesis of Embedded Software. J. Softw. 4(7): 717-727 (2009) - [j46]Andreas Gerstlauer, Christian Haubelt
, Andy D. Pimentel
, Todor P. Stefanov
, Daniel D. Gajski, Jürgen Teich:
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1517-1530 (2009) - [c160]Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski:
Hardware-dependent software synthesis for many-core embedded systems. ASP-DAC 2009: 304-310 - 2008
- [j45]Rainer Dömer
, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski:
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008) - [j44]Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs. ACM Trans. Reconfigurable Technol. Syst. 1(2): 11:1-11:21 (2008) - [j43]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 466-475 (2008) - [c159]Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). DAC 2008: 72-75 - [c158]Bita Gorjiara, Daniel Gajski:
Automatic architecture refinement techniques for customizing processing elements. DAC 2008: 379-384 - [c157]Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara:
Specify-explore-refine (SER): from specification to implementation. DAC 2008: 586-591 - [c156]Yonghyun Hwang, Samar Abdi, Daniel Gajski:
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. DATE 2008: 3-8 - [c155]Jelena Trajkovic
, Daniel D. Gajski:
Custom Processor Core Construction from C Code. SASP 2008: 1-6 - [c154]Daniel D. Gajski, Samar Abdi, Ines Viskic:
Model Based Synthesis of Embedded Software. SEUS 2008: 21-33 - 2007
- [j42]Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1676-1687 (2007) - [c153]Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil:
TLM: Crossing Over From Buzz To Adoption. DAC 2007: 444-445 - [c152]Mehrdad Reshadi, Daniel Gajski:
Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. DATE 2007: 1337-1342 - [c151]Daniel D. Gajski:
New Strategies for System-Level Design. DDECS 2007: 15 - [c150]Bita Gorjiara, Daniel Gajski:
FPGA-friendly code compression for horizontal microcoded custom IPs. FPGA 2007: 108-115 - [c149]Bita Gorjiara, Daniel Gajski:
A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. ICCD 2007: 609-614 - [c148]Jelena Trajkovic
, Daniel Gajski:
Automatic Data Path Generation from C code for Custom Processors. IESS 2007: 107-120 - [c147]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144 - [c146]Hansu Cho, Samar Abdi, Daniel Gajski:
Interface synthesis for heterogeneous multi-core systems from transaction level models. LCTES 2007: 140-142 - [c145]Ines Viskic, Samar Abdi, Daniel D. Gajski:
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. LCTES 2007: 143-145 - 2006
- [j41]Samar Abdi, Daniel Gajski:
Verification of System Level Model Transformations. Int. J. Parallel Program. 34(1): 29-59 (2006) - [c144]Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski:
Designing a custom architecture for DCT using NISC technology. ASP-DAC 2006: 116-117 - [c143]Hansu Cho, Samar Abdi, Daniel Gajski:
Design and implementation of transducer for ARM-TMS communication. ASP-DAC 2006: 126-127 - [c142]Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69 - [c141]Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski:
Generic netlist representation for system and PE level design exploration. CODES+ISSS 2006: 282-287 - [c140]Jelena Trajkovic
, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
A Graph Based Algorithm for Data Path Optimization in Custom Processors. DSD 2006: 496-503 - [c139]Samar Abdi, Daniel Gajski:
Transaction Routing and its Verification by Correct Model Transformations. HLDVT 2006: 129-136 - [c138]Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . ICCD 2006: 356-361 - 2005
- [c137]Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48 - [c136]Samar Abdi, Daniel Gajski:
A formalism for functionality preserving system level transformations. ASP-DAC 2005: 139-144 - [c135]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Multi-metric and multi-entity characterization of applications for early system design exploration. ASP-DAC 2005: 944-947 - [c134]Junyu Peng, Samar Abdi, Daniel Gajski:
A clustering technique to optimize hardware/software synchronization. ASP-DAC 2005: 965-968 - [c133]Mehrdad Reshadi, Daniel Gajski:
A cycle-accurate compilation algorithm for custom pipelined datapaths. CODES+ISSS 2005: 21-26 - [c132]Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser:
What will system level design be when it grows up? CODES+ISSS 2005: 123 - [c131]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260 - [c130]Samar Abdi, Daniel D. Gajski:
Functional Validation of System Level Static Scheduling. DATE 2005: 542-547 - [c129]Shuqing Zhao, Daniel D. Gajski:
Defining an Enhanced RTL Semantics. DATE 2005: 548-553 - [c128]Bita Gorjiara, Daniel D. Gajski:
Custom Processor Design Using NISC: A Case-Study on DCT algorithm. ESTIMedia 2005: 55-60 - [c127]Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski:
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ICCD 2005: 69-76 - [c126]Haobo Yu, Rainer Dömer, Daniel D. Gajski:
Software and Driver Synthesis from Transaction Level Models. IESS 2005: 65-76 - [c125]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic Generation of Communication Architectures. IESS 2005: 179-188 - [c124]Shuqing Zhao, Daniel D. Gajski:
Structural operational semantics for supporting multi-cycle operations in RTL HDLs. MEMOCODE 2005: 45-53 - [c123]Daniel Gajski:
System design extreme makeover. MEMOCODE 2005: 71-75 - 2004
- [c122]Samar Abdi, Daniel Gajski:
On deriving equivalent architecture model from system specification. ASP-DAC 2004: 322-327 - [c121]Haobo Yu, Rainer Dömer, Daniel Gajski:
Embedded software generation from system level design languages. ASP-DAC 2004: 463-468 - [c120]Dongwan Shin, Samar Abdi, Daniel Gajski:
Automatic generation of bus functional models from transaction level models. ASP-DAC 2004: 756-758 - [c119]Lukai Cai, Haobo Yu, Daniel Gajski:
A novel memory size model for variable-mapping in system level design. ASP-DAC 2004: 812-817 - [c118]Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist:
Embedded systems education: how to teach the required skills? CODES+ISSS 2004: 254-255 - [c117]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Retargetable profiling for rapid, early system-level design space exploration. DAC 2004: 281-286 - [c116]Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon:
Were the good old days all that good?: EDA then and now. DAC 2004: 543 - [c115]Samar Abdi, Daniel Gajski:
Automatic generation of equivalent architecture model from functional specification. DAC 2004: 608-613 - [c114]Samar Abdi, Daniel Gajski:
Model validation for mapping specification behaviors to processing elements. HLDVT 2004: 101-106 - 2003
- [c113]Lukai Cai, Daniel Gajski:
Transaction level modeling: an overview. CODES+ISSS 2003: 19-24 - [c112]Haobo Yu, Andreas Gerstlauer, Daniel Gajski:
RTOS scheduling in transaction level models. CODES+ISSS 2003: 31-36 - [c111]Samar Abdi, Dongwan Shin, Daniel Gajski:
Automatic communication refinement for system level design. DAC 2003: 300-305 - [c110]Andreas Gerstlauer, Haobo Yu, Daniel Gajski:
RTOS Modeling for System Level Design. DATE 2003: 10130-10135 - [c109]Heinz-Josef Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel:
Transaction Based Design: Another Buzzword or the Solution to a Design Problem? DATE 2003: 10876-10879 - [p1]Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski:
RTOS Modeling for System Level Design. Embedded Software for SoC 2003: 55-68 - 2002
- [j40]Jianwen Zhu, Daniel D. Gajski:
An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 363-373 (2002) - [c108]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Co-design of embedded controllers for power electronics and electric systems. ISIC 2002: 379-383 - [c107]Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez:
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. DATE 2002: 1137 - [c106]Shuqing Zhao, Daniel Gajski:
Modeling a new RTL semantics in C++. ISCAS (5) 2002: 741-744 - [c105]Daniel Gajski, Junyu Peng:
Optimal Message-Passing for Data Coherency in Distributed Architecture. ISSS 2002: 20-25 - [c104]Daniel Gajski, Andreas Gerstlauer:
System-Level Abstraction Semantics. ISSS 2002: 231-236 - [c103]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Seamless approach for the design of control systems for power electronics and electric drives. SMC 2002: 6 - [c102]Junyu Peng, Samar Abdi, Daniel Gajski:
Automatic Model Refinement for Fast Architecture Exploration. ASP-DAC/VLSI Design 2002: 332-337 - 2001
- [b2]Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski:
System Design - A Practical Guide with SpecC. Springer 2001, ISBN 978-0-7923-7387-2, pp. 1-255 - [j39]Smita Bakshi, Daniel Gajski:
Performance-constrained hierarchical pipelining for behaviors, loops, and operations. ACM Trans. Design Autom. Electr. Syst. 6(1): 1-25 (2001) - [c101]Jianwen Zhu, Daniel Gajski:
Compiling SpecC for simulation. ASP-DAC 2001: 57-62 - [c100]Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
:
Panel: The Next HDL: If C++ is the Answer, What was the Question? DAC 2001: 71-72 - [c99]Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong:
C/C++: progress or deadlock in system-level specification. DATE 2001: 136-137 - [c98]Lukai Cai, Daniel Gajski, Mike Olivarez:
Introduction of system level architecture exploration using the SpecC methodology. ISCAS (5) 2001: 9-12 - [c97]Brian Bailey, Daniel Gajski:
RTL semantics and methodology. ISSS 2001: 69-74 - 2000
- [c96]Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud:
Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42 - [c95]Nong Fan, Viraphol Chaiyakul, Daniel Gajski:
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. ASP-DAC 2000: 43-48 - [c94]Rainer Dömer, Daniel Gajski:
Reuse and protection of intellectual property in the SpecC system. ASP-DAC 2000: 49-54 - [c93]Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
:
One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654 - [c92]Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann:
The Specification Language SpecC within the PARADISE Design Environment. DIPES 2000: 111-120
1990 – 1999
- 1999
- [j38]Smita Bakshi, Daniel D. Gajski:
Partitioning and pipelining for performance-constrained hardware/software systems. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 419-432 (1999) - [c91]Jianwen Zhu, Daniel Gajski:
A unified formal model of ISA and FSMD. CODES 1999: 121-125 - [c90]Daniel Gajski:
IP-based Design Methodology. DAC 1999: 43 - [c89]Jianwen Zhu, Daniel Gajski:
Soft Scheduling in High Level Synthesis. DAC 1999: 219-224 - [c88]Jianwen Zhu, Daniel Gajski:
OpenJ: An Extensible System Level Design Language. DATE 1999: 480-484 - [c87]Dai Araki, Tadatoshi Ishii, Daniel Gajski:
Rapid Prototyping with HW/SW Codesign Tool. ECBS 1999: 114-121 - [c86]Daniel Gajski, Reinaldo A. Bergamaschi:
Panel Statement: System-Level Design: Designers' Wish List vs. Reality. ISSS 1999: 8-9 - 1998
- [j37]Rainer Dömer, Daniel D. Gajski, Jianwen Zhu:
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40(3): 7-12 (1998) - [j36]Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 84-100 (1998) - [c85]Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
System-level exploration with SpecSyn. DAC 1998: 812-817 - [c84]Smita Bakshi, Daniel D. Gajski:
Hierarchical pipelining for behaviors, loops, and operations. ICCD 1998: 450-455 - [c83]Daniel Gajski, Rainer Dömer, Jianwen Zhu:
IP-Centric Methodology and Specification Language. DIPES 1998: 3-22 - 1997
- [j35]Jie Gong, Daniel Gajski, Smita Bakshi:
Model refinement for hardware-software codesign. ACM Trans. Design Autom. Electr. Syst. 2(1): 22-41 (1997) - [c82]Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski:
A quantitative analysis for optimizing memory allocation. ASP-DAC 1997: 239-245 - [c81]Smita Bakshi, Daniel Gajski:
Hardware/Software Partitioning and Pipelining. DAC 1997: 713-716 - [c80]Smita Bakshi, Daniel Gajski:
A Scheduling and Pipelining Algorithm for Hardware/Software Systems. ISSS 1997: 113- - 1996
- [j34]En-Shou Chang, Daniel Gajski, Sanjiv Narayan:
An optimal clock period selection method based on slack minimization criteria. ACM Trans. Design Autom. Electr. Syst. 1(3): 352-370 (1996) - [j33]Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung:
System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 70-82 (1996) - [j32]Smita Bakshi, Daniel D. Gajski:
Component selection for high-performance pipelines. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 181-194 (1996) - [c79]Jie Gong, Daniel D. Gajski, Smita Bakshi:
Model Refinement for Hardware-Software Codesign. ED&TC 1996: 270-274 - [c78]Sanjiv Narayan, Daniel D. Gajski:
Rapid performance estimation for system design. EURO-DAC 1996: 206-211 - [c77]Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski:
Clock optimization for high-performance pipelined design. EURO-DAC 1996: 330-335 - [c76]Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan:
Component selection in resource shared and pipelined DSP applications. EURO-DAC 1996: 370-375 - [c75]Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul:
Clock-driven performance optimization in interactive behavioral synthesis. ICCAD 1996: 154-157 - [c74]Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi:
Opportunities and pitfalls in HDL-based system design. ICCD 1996: 56-57 - 1995
- [j31]Daniel D. Gajski, Frank Vahid:
Specification and Design of Embedded Hardware-Software Systems. IEEE Des. Test Comput. 12(1): 53-67 (1995) - [j30]Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 694-706 (1995) - [j29]Frank Vahid, Daniel D. Gajski:
Incremental hardware estimation during hardware/software functional partitioning. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 459-464 (1995) - [j28]Jie Gong, Daniel D. Gajski, Alexandru Nicolau:
Performance evaluation for application-specific architectures. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 483-490 (1995) - [c73]