default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDAlexander V. Veidenbaum
Person information
- affiliation: University of California, Irvine, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j29]Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Hyperdimensional computing: a framework for stochastic computation and symbolic AI. J. Big Data 11(1): 145 (2024)- 2023
- [j28]Mike Heddes, Igor Nunes, Pere Vergés, Denis Kleyko, Danny Abraham, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures. J. Mach. Learn. Res. 24: 255:1-255:10 (2023) - [c117]Marc Titus Trifan, Alexandru Nicolau, Alexander V. Veidenbaum:
Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE. CSCloud/EdgeCom 2023: 46-52 - [c116]Neftali Watkinson, Divya Devineni, Victor Joe, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Using Hyperdimensional Computing to Extract Features for the Detection of Type 2 Diabetes. IPDPS Workshops 2023: 149-156 - [c115]Igor Nunes
, Mike Heddes, Pere Vergés, Danny Abraham, Alexander V. Veidenbaum, Alex Nicolau, Tony Givargis:
DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication. KDD 2023: 1758-1769 - [i7]Igor Nunes, Mike Heddes, Pere Vergés, Danny Abraham, Alexander V. Veidenbaum, Alexandru Nicolau, Tony Givargis:
DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication. CoRR abs/2305.17310 (2023) - [i6]Marc Titus Trifan, Alexandru Nicolau, Alexander V. Veidenbaum:
Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE. IACR Cryptol. ePrint Arch. 2023: 568 (2023) - 2022
- [c114]Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Hyperdimensional hashing: a robust and efficient dynamic hash table. DAC 2022: 907-912 - [c113]Igor Nunes, Mike Heddes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
GraphHD: Efficient graph classification using hyperdimensional computing. DATE 2022: 1485-1490 - [c112]Mihnea Chirila, Paolo D'Alberto, Hsin-Yu Ting, Alexander V. Veidenbaum, Alexandru Nicolau:
A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAs. ISQED 2022: 108-113 - [i5]Igor Nunes, Mike Heddes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
GraphHD: Efficient graph classification using hyperdimensional computing. CoRR abs/2205.07826 (2022) - [i4]Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table. CoRR abs/2205.07850 (2022) - 2021
- [c111]Neftali Watkinson, Tony Givargis, Victor Joe, Alexandru Nicolau, Alexander V. Veidenbaum:
Class-Modeling of Septic Shock With Hyperdimensional Computing. EMBC 2021: 1653-1659 - [c110]Neftali Watkinson, Tony Givargis, Victor Joe, Alexandru Nicolau, Alexander V. Veidenbaum:
Detecting COVID-19 Related Pneumonia On CT Scans Using Hyperdimensional Computing. EMBC 2021: 3970-3973 - 2020
- [c109]Neftali Watkinson, Preston Tai, Alexandru Nicolau, Alexander V. Veidenbaum:
NumbaSummarizer: A Python Library for Simplified Vectorization Reports. IPDPS Workshops 2020: 269-275
2010 – 2019
- 2019
- [c108]Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau:
AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms. FPGA 2019: 252-261 - [c107]Neftali Watkinson, Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum:
Teaching Parallel Computing and Dependence Analysis with Python. IPDPS Workshops 2019: 320-325 - [c106]Gongjin Sun, Junjie Shen, Alexander V. Veidenbaum:
Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance. IPDPS 2019: 953-962 - [i3]Aniket Shivam, Neftali Watkinson, Alexandru Nicolau, David A. Padua, Alexander V. Veidenbaum:
Towards an Achievable Performance for the Loop Nests. CoRR abs/1902.00603 (2019) - [i2]Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum:
MCompiler: A Synergistic Compilation Framework. CoRR abs/1905.12755 (2019) - 2018
- [j27]Zhangxiaowen Gong, Zhi Chen, Justin Josef Szaday, David C. Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, Josep Torrellas:
An empirical study of the effect of source-level loop transformations on compiler stability. Proc. ACM Program. Lang. 2(OOPSLA): 126:1-126:29 (2018) - [c105]Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau:
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines. FCCM 2018: 227 - [c104]Junjie Shen, Zhi Chen, Nahid Farhady Ghalaty, Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum:
New Opportunities for Compilers in Computer Security. LCPC 2018: 54-60 - [c103]Aniket Shivam, Neftali Watkinson, Alexandru Nicolau, David A. Padua, Alexander V. Veidenbaum:
Towards an Achievable Performance for the Loop Nests. LCPC 2018: 70-77 - [c102]Sajjad Taheri, Alexander V. Veidenbaum, Alexandru Nicolau, Ningxin Hu, Mohammad R. Haghighat:
OpenCV.js: computer vision processing for the open web platform. MMSys 2018: 478-483 - 2017
- [j26]Amir-Mohammad Rahmani, Pasi Liljeberg, José Luis Ayala, Hannu Tenhunen, Alexander V. Veidenbaum:
Special issue on energy efficient multi-core and many-core systems, Part II. J. Parallel Distributed Comput. 100: 128-129 (2017) - [c101]Zhi Chen, Junjie Shen, Alex Nicolau, Alexander V. Veidenbaum, Nahid Farhady Ghalaty, Rosario Cammarota:
CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization. FDTC 2017: 57-64 - [c100]Zhi Chen, Zhangxiaowen Gong, Justin Josef Szaday, David C. Wong, David A. Padua, Alexandru Nicolau, Alexander V. Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, Gerald DeJong:
LORE: A loop repository for the evaluation of compilers. IISWC 2017: 219-228 - [c99]Neftali Watkinson, Aniket Shivam, Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, Zhangxiaowen Gong:
Using Hardware Counters to Predict Vectorization. LCPC 2017: 3-16 - [i1]Zhi Chen, Junjie Shen, Alex Nicolau, Alexander V. Veidenbaum, Nahid Farhady Ghalaty, Rosario Cammarota:
CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization. IACR Cryptol. ePrint Arch. 2017: 1083 (2017) - 2016
- [j25]Amir-Mohammad Rahmani, Pasi Liljeberg, José Luis Ayala, Hannu Tenhunen, Alexander V. Veidenbaum:
Special issue on energy efficient multi-core and many-core systems, Part I. J. Parallel Distributed Comput. 95: 1-2 (2016) - [c98]Zhi Chen, Alexandru Nicolau, Alexander V. Veidenbaum:
SIMD-based soft error detection. Conf. Computing Frontiers 2016: 45-54 - [c97]Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum, Mario Mango Furnari, Rosario Cammarota:
Polygonal Iteration Space Partitioning. LCPC 2016: 121-136 - [c96]Siavash Rezaei, César-Alejandro Hernández-Calderón, Saeed Mirzamohammadi, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alex Nicolau, Michael J. Prather:
Data-rate-aware FPGA-based acceleration framework for streaming applications. ReConFig 2016: 1-6 - 2015
- [c95]Sajjad Taheri, Laleh Aghababaie Beni, Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, Jianlin Qiu, Qiang Lu, Mohammad R. Haghighat:
WebRTCbench: a benchmark for performance assessment of webRTC implementations. ESTIMedia 2015: 1-7 - [c94]Zhi Chen, Ryoichi Inagaki, Alexandru Nicolau, Alexander V. Veidenbaum:
Software fault tolerance for FPUs via vectorization. SAMOS 2015: 203-210 - 2014
- [c93]Taesu Kim, Dali Zhao, Alexander V. Veidenbaum:
Multiple stream tracker: a new hardware stride prefetcher. Conf. Computing Frontiers 2014: 34:1-34:10 - [c92]Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum:
Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies. ICS 25th Anniversary 2014: 9-11 - [c91]Yizhuo Wang, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum, Rosario Cammarota:
A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms. NPC 2014: 459-470 - [c90]Carlo Galuzzi, Alexander V. Veidenbaum:
Preface. ICSAMOS 2014: 1 - [c89]Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum:
Dynamic-vector execution on a general purpose EDGE chip multiprocessor. ICSAMOS 2014: 18-25 - 2013
- [j24]Nam Duong, Alexander V. Veidenbaum:
Compiler-Assisted, Selective Out-Of-Order Commit. IEEE Comput. Archit. Lett. 12(1): 21-24 (2013) - [c88]Rosario Cammarota, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum:
Optimizing Program Performance via Similarity, Using a Feature-Agnostic Approach. APPT 2013: 199-213 - [c87]Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum, Arun Kejariwal, Debora Donato, Mukund Madhugiri:
On the Determination of Inlining Vectors for Program Optimization. CC 2013: 164-183 - [c86]Rosario Cammarota, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum:
Effective Evaluation of Multi-core Based Systems. ISPDC 2013: 19-25 - [c85]Dali Zhao, Houman Homayoun, Alexander V. Veidenbaum:
Temperature aware thread migration in 3D architecture with stacked DRAM. ISQED 2013: 80-87 - 2012
- [c84]Nam Duong, Taesu Kim, Dali Zhao, Alexander V. Veidenbaum:
Revisiting level-0 caches in embedded processors. CASES 2012: 171-180 - [c83]Rosario Cammarota, Arun Kejariwal, Debora Donato, Alexandru Nicolau, Alexander V. Veidenbaum:
Selective search of inlining vectors for program optimization. Conf. Computing Frontiers 2012: 257-260 - [c82]Yizhuo Wang, Alexandru Nicolau, Rosario Cammarota, Alexander V. Veidenbaum:
A fault tolerant self-scheduling scheme for parallel loops on shared memory systems. HiPC 2012: 1-10 - [c81]Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum:
Just in Time Load Balancing. LCPC 2012: 1-16 - [c80]Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum:
Improving Cache Management Policies Using Dynamic Reuse Distances. MICRO 2012: 389-400 - 2011
- [j23]Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi:
On leakage power optimization in clock tree networks for ASICs and general-purpose processors. Sustain. Comput. Informatics Syst. 1(1): 75-87 (2011) - [j22]Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum:
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2081-2094 (2011) - [j21]Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari:
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2303-2316 (2011) - [c79]Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau:
Pruning hardware evaluation space via correlation-driven application similarity analysis. Conf. Computing Frontiers 2011: 4 - 2010
- [c78]Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos:
Exploitation of nested thread-level speculative parallelism on multi-core systems. Conf. Computing Frontiers 2010: 99-100 - [c77]Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt:
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. Conf. Computing Frontiers 2010: 297-308 - [c76]Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil D. Dutt:
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. HiPEAC 2010: 216-231 - [c75]Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum:
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED 2010: 49-54 - [c74]Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi:
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. ISQED 2010: 499-507 - [c73]Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos:
On the efficacy of call graph-level thread-level speculation. WOSP/SIPEW 2010: 247-248 - [e4]Kazuki Joe, Alexander V. Veidenbaum:
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2010, Hilo, Kohala Coast, HI, USA, January 17-19, 2010. IEEE 2010, ISBN 978-0-7695-4396-3 [contents]
2000 – 2009
- 2009
- [j20]Jayram Moorkanikara Nageswaran, Andrew Felch, Ashok Chandrasekhar, Nikil D. Dutt, Richard Granger, Alex Nicolau, Alexander V. Veidenbaum:
Brain Derived Vision Algorithm on High Performance Architectures. Int. J. Parallel Program. 37(4): 345-369 (2009) - [j19]Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum:
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks 22(5-6): 791-800 (2009) - [j18]Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito:
On the exploitation of loop-level parallelism in embedded applications. ACM Trans. Embed. Comput. Syst. 8(2): 10:1-10:34 (2009) - [c72]Arun Kejariwal, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos:
Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. ICPP 2009: 74-83 - [c71]Alexandru Nicolau, Guangqiang Li, Alexander V. Veidenbaum, Arun Kejariwal:
Synchronization optimizations for efficient execution on multi-cores. ICS 2009: 169-180 - [c70]Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum:
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. IJCNN 2009: 2145-2152 - [c69]Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum:
Power-aware load balancing of large scale MPI applications. IPDPS 2009: 1-8 - [c68]Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy:
Performance Characterization of Itanium® 2-Based Montecito Processor. SPEC Benchmark Workshop 2009: 36-56 - [c67]Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos:
Cache-aware partitioning of multi-dimensional iteration spaces. SYSTOR 2009: 15 - [e3]Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum:
Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009. ACM 2009, ISBN 978-1-60558-413-3 [contents] - 2008
- [j17]José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum:
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. Int. J. Embed. Syst. 3(4): 285-293 (2008) - [j16]Juan L. Aragón, Alexander V. Veidenbaum:
Optimizing CAM-based instruction cache designs for low-power embedded systems. J. Syst. Archit. 54(12): 1155-1163 (2008) - [j15]Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal:
Improving SDRAM access energy efficiency for low-power embedded systems. ACM Trans. Embed. Comput. Syst. 7(3): 24:1-24:21 (2008) - [c66]Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum:
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. CASES 2008: 197-206 - [c65]Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum:
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. DAC 2008: 68-71 - [c64]Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot:
Adaptive techniques for leakage power management in L2 cache peripheral circuits. ICCD 2008: 563-569 - [c63]Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum:
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. ICCD 2008: 699-706 - [c62]Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36 - [c61]Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum:
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. LCTES 2008: 23-30 - [c60]Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum:
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. LCTES 2008: 71-78 - [c59]Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero:
A distributed processor state management architecture for large-window processors. MICRO 2008: 11-22 - [c58]Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos:
Cache-aware iteration space partitioning. PPoPP 2008: 269-270 - [c57]Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Xinmin Tian, Milind Girkar, Hideki Saito, Utpal Banerjee:
Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. ICSAMOS 2008: 132-141 - [c56]Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum:
A centralized cache miss driven technique to improve processor power dissipation. ICSAMOS 2008: 195-202 - 2007
- [j14]Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau:
A predictive decode filter cache for reducing power consumption in embedded processors. ACM Trans. Design Autom. Electr. Syst. 12(2): 14 (2007) - [c55]Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum:
A simplified java bytecode compilation system for resource-constrained embedded processors. CASES 2007: 218-228 - [c54]Houman Homayoun, Alexander V. Veidenbaum:
Reducing leakage power in peripheral circuits of L2 caches. ICCD 2007: 230-237 - [c53]Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger:
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. PARCO 2007: 767-776 - [c52]Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos:
Tight analysis of the performance potential of thread speculation using spec CPU 2006. PPoPP 2007: 215-225 - [c51]Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum:
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. SIGMETRICS 2007: 361-362 - 2006
- [c50]Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito:
Challenges in exploitation of loop parallelism in embedded applications. CODES+ISSS 2006: 173-180 - [c49]Milind Girkar, Arun Kejariwal, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos:
Probablistic Self-Scheduling. Euro-Par 2006: 253-264 - [c48]Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum:
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. ICCD 2006: 101-107 - [c47]Arun Kejariwal, Xinmin Tian, Wei Li, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos:
On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. ICS 2006: 24 - 2005
- [j13]Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta:
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. IEEE Trans. Computers 54(2): 185-197 (2005) - [c46]Juan L. Aragón, Alexander V. Veidenbaum:
Energy-Effective Instruction Fetch Unit for Wide Issue Processors. Asia-Pacific Computer Systems Architecture Conference 2005: 15-27 - [c45]Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau:
High performance annotation-aware JVM for Java cards. EMSOFT 2005: 52-61 - [c44]Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luís Villa:
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. ICCD 2005: 647-653 - [c43]Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum:
An asymmetric clustered processor based on value content. ICS 2005: 61-70 - [c42]Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero:
Decoupled State-Execute Architecture. ISHPC 2005: 68-78 - [c41]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Using a Way Cache to Improve Performance of Set-Associative Caches. ISHPC 2005: 93-104 - 2004
- [j12]Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luís Villa:
A partitioned instruction queue to reduce instruction wakeup energy. Int. J. High Perform. Comput. Netw. 1(4): 153-161 (2004) - [j11]Alexander V. Veidenbaum:
Guest Editor's Introduction: Application-Specific Processors. IEEE Micro 24(3): 8-9 (2004) - [c40]Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu:
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. DATE 2004: 1374-1375 - [c39]Alexander V. Veidenbaum, Dan Nicolaescu:
Low Energy, Highly-Associative Cache Design for Embedded Processors. ICCD 2004: 332-335 - [c38]Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero:
A Content Aware Integer Register File Organization. ISCA 2004: 314-324 - [c37]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Caching Values in the Load Store Queue. MASCOTS 2004: 580-587 - [c36]Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero:
An Optimized Front-End Physical Register File with Banking and Writeback Filtering. PACS 2004: 1-14 - 2003
- [j10]Alex Orailoglu, Alexander V. Veidenbaum:
Guest Editors' Introduction: Application-Specific Microprocessors. IEEE Des. Test Comput. 20(1): 6-7 (2003) - [j9]José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo:
Power-Aware Compilation for Register File Energy Reduction. Int. J. Parallel Program. 31(6): 451-467 (2003) - [c35]José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez:
Energy Aware Register File Implementation through Instruction Predecode. ASAP 2003: 86-96 - [c34]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. DATE 2003: 11064-11069 - [c33]Sudeep Pasricha, Alexander V. Veidenbaum:
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. ICCD 2003: 526-531 - [c32]Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luís Villa, Mateo Valero:
A Simple Low-Energy Instruction Wakeup Mechanism. ISHPC 2003: 99-112 - [c31]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Reducing data cache energy consumption via cached load/store queue. ISLPED 2003: 252-257 - [c30]Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum:
A Data Cache with Dynamic Mapping. LCPC 2003: 436-450 - [p1]Dan Nicolaescu, Alexander V. Veidenbaum, Alex Nicolau:
Low Energy Associative Data Caches for Embedded Systems. Embedded Software for SoC 2003: 513-525 - [e2]Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso:
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings. Lecture Notes in Computer Science 2858, Springer 2003, ISBN 3-540-20359-1 [contents] - 2002
- [j8]Alexander V. Veidenbaum:
Guest Editor's Introduction. Int. J. Parallel Program. 30(4): 223-224 (2002) - [c29]Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau:
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE 2002: 168-175 - [c28]Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. ISHPC 2002: 120-132 - 2001
- [j7]Alexander V. Veidenbaum:
Guest Editor's Introduction. Int. J. Parallel Program. 29(5): 461-462 (2001) - 2000
- [j6]Sunil Kim, Alexander V. Veidenbaum:
On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors. J. Supercomput. 16(3): 197-216 (2000) - [c27]Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Compiler-Directed Cache Line Size Adaptivity. Intelligent Memory Systems 2000: 183-187 - [c26]Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Compiler-Directed Cache Assist Adaptivity. ISHPC 2000: 88-104 - [e1]John Reynders, Alexander V. Veidenbaum:
Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000. ACM 2000, ISBN 1-58113-270-0 [contents]
1990 – 1999
- 1999
- [j5]Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer:
Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors. Int. J. High Speed Comput. 10(1): 115-140 (1999) - [j4]Edward H. Gornish, Alexander V. Veidenbaum:
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. Int. J. Parallel Program. 27(1): 35-70 (1999) - [j3]Sunil Kim, Alexander V. Veidenbaum:
Interconnection network organization and its impact on performance and cost in shared memory multiprocessors. Parallel Comput. 25(3): 283-309 (1999) - [c25]Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji:
Adapting cache line size to application behavior. International Conference on Supercomputing 1999: 145-154 - 1998
- [c24]Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan:
Retrospective: The Cedar System. 25 Years ISCA: Retrospectives and Reprints 1998: 89-91 - 1997
- [c23]Sunil Kim, Alexander V. Veidenbaum:
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems. IEEE PACT 1997: 40-51 - [c22]Sunil Kim, Alexander V. Veidenbaum:
Stride-directed Prefetching for Secondary Caches. ICPP 1997: 314-323 - [c21]Alexander V. Veidenbaum:
Instruction Cache Prefetching Using Multilevel Branch Prediction. ISHPC 1997: 51-70 - 1995
- [j2]Elana D. Granston, Alexander V. Veidenbaum:
Combining flow and dependence analyses to expose redundant array accesses. Int. J. Parallel Program. 23(5): 423-470 (1995) - [c20]Sunil Kim, Alexander V. Veidenbaum:
On Shortest Path Routing in Single Stage Shuffle-Exchange Networks. SPAA 1995: 298-307 - 1994
- [c19]Edward H. Gornish, Alexander V. Veidenbaum:
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. ICPP (2) 1994: 281-284 - [c18]Stephen W. Turner, Alexander V. Veidenbaum:
Scalability of the Cedar system. SC 1994: 247-254 - 1993
- [c17]Yung-Chin Chen, Alexander V. Veidenbaum:
Performance Evaluation of Memory Caches in Multiprocessors. ICPP (1) 1993: 184-187 - [c16]David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner:
The Cedar System and an Initial Performance Study. ISCA 1993: 213-223 - 1992
- [c15]Yung-Chin Chen, Alexander V. Veidenbaum:
An Effective Write Policy for Software Coherence Schemes. SC 1992: 661-672 - 1991
- [c14]Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter:
The Organization of the Cedar System. ICPP (1) 1991: 49-56 - [c13]Kyle A. Gallivan, William Jalby, Stephen W. Turner, Alexander V. Veidenbaum, Harry A. G. Wijshoff:
Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. ICPP (1) 1991: 71-75 - [c12]Elana D. Granston, Alexander V. Veidenbaum:
An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. ICPP (2) 1991: 83-90 - [c11]Yung-Chin Chen, Alexander V. Veidenbaum:
A software coherence scheme with the assistance of directories. ICS 1991: 284-294 - [c10]John D. Bruner, Hoichi Cheong, Alexander V. Veidenbaum, Pen-Chung Yew:
Chief: A Parallel Simulation Environment for Parallel Systems. IPPS 1991: 568-575 - [c9]Yung-Chin Chen, Alexander V. Veidenbaum:
Comparison and analysis of software and directory coherence schemes. SC 1991: 818-829 - [c8]Elana D. Granston, Alexander V. Veidenbaum:
Detecting redundant accesses to array data. SC 1991: 854-865 - 1990
- [j1]Hoichi Cheong, Alexander V. Veidenbaum:
Compiler-Directed Cache Management in Multiprocessors. Computer 23(6): 39-47 (1990) - [c7]Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum:
Compiler-directed data prefetching in multiprocessors with memory hierarchies. ICS 1990: 354-368
1980 – 1989
- 1989
- [c6]Hoichi Cheong, Alexander V. Veidenbaum:
A version control approach to Cache coherence. ICS 1989: 322-330 - 1988
- [c5]Hoichi Cheong, Alexander V. Veidenbaum:
Stale Data Detection and Coherence Enforcement Using Flow Analysis. ICPP (1) 1988: 138-145 - [c4]Stephen W. Turner, Alexander V. Veidenbaum:
Performance of a shared memory system for vector multiprocessors. ICS 1988: 315-325 - [c3]Hoichi Cheong, Alexander V. Veidenbaum:
A Cache Coherence Scheme With Fast Selective Invalidation. ISCA 1988: 299-307 - 1987
- [c2]Hoichi Cheong, Alexander V. Veidenbaum:
The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs. ICS 1987: 316-337 - 1986
- [c1]Alexander V. Veidenbaum:
A Compiler-Assisted Cache Coherence Solution for Multiprcessors. ICPP 1986: 1029-1036
Coauthor Index
Alexandru Nicolau
aka: Alex Nicolau
aka: Alex Nicolau
[j29] [j28] [c117] [c116] [c115] [i7] [i6] [c114] [c113] [c112] [i5] [i4] [c111] [c110] [c109] [c108] [c107] [i3] [i2] [j27] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [i1] [c98] [c97] [c96] [c95] [c94] [c91] [c88] [c87] [c86] [c83] [c82] [c81] [c79] [c78] [c73] [j20] [j19] [j18] [c72] [c71] [c70] [c68] [c67] [c61] [c58] [c57] [j14] [c55] [c53] [c52] [c51] [c50] [c49] [c47] [j13] [c45] [c41] [c37] [c34] [c31] [c30] [p1] [c29] [c28] [c27] [c26] [c25]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-21 21:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
