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ORCIDIsmet Bayraktaroglu
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2020 – today
- 2023
[i1]Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren:
ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR abs/2311.00176 (2023)
2000 – 2009
- 2006
- [c26]Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins:
Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues. ITC 2006: 1-7 - 2005
- [j8]Ismet Bayraktaroglu, Alex Orailoglu:
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. IEEE Trans. Computers 54(1): 61-75 (2005) - [c25]Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu:
Microprocessor silicon debug based on failure propagation tracing. ITC 2005: 10 - [c24]Ismet Bayraktaroglu, Olivier Caty, Yickkei Wong:
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. VTS 2005: 21-26 - 2004
- [j7]Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu:
Seamless Test of Digital Components in Mixed-Signal Paths. IEEE Des. Test Comput. 21(1): 44-55 (2004) - [j6]Yiorgos Makris
, Ismet Bayraktaroglu, Alex Orailoglu:
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. IEEE Trans. Reliab. 53(2): 269-278 (2004) - [c23]Ismet Bayraktaroglu, Manuel d'Abreu:
ATPG based functional test for data paths: application to a floating point unit. HLDVT 2004: 37-40 - 2003
- [j5]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electron. Test. 19(4): 457-467 (2003) - [j4]Ismet Bayraktaroglu, Alex Orailoglu:
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. IEEE Trans. Computers 52(11): 1480-1489 (2003) - [c22]Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu:
Test application time and volume compression through seed overlapping. DAC 2003: 732-737 - [c21]Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan:
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. ITC 2003: 961-970 - [c20]Ismet Bayraktaroglu, Alex Orailoglu:
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. VTS 2003: 113-120 - 2002
- [j3]Ismet Bayraktaroglu, Alex Orailoglu:
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. IEEE Des. Test Comput. 19(1): 42-53 (2002) - [c19]Ismet Bayraktaroglu, Alex Orailoglu:
Gate Level Fault Diagnosis in Scan-Based BIST. DATE 2002: 376-381 - [c18]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Dynamic test data transformations for average and peak power reductions. ETW 2002: 113-118 - [c17]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC 2002: 844-850 - [c16]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions. VTS 2002: 166-172 - 2001
- [j2]Ismet Bayraktaroglu, Alex Orailoglu:
Concurrent test for digital linear systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1132-1142 (2001) - [c15]Ismet Bayraktaroglu, Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? Asian Test Symposium 2001: 373-378 - [c14]Ismet Bayraktaroglu, Alex Orailoglu:
Test Volume and Application Time Reduction Through Scan Chain Concealment. DAC 2001: 151-155 - [c13]Ismet Bayraktaroglu, Alex Orailoglu:
Diagnosis for scan-based BIST: reaching deep into the signatures. DATE 2001: 102-111 - [c12]Ismet Bayraktaroglu, Alex Orailoglu:
Improved Methods for Fault Diagnosis in Scan-Based BIST. LATW 2001: 169-172 - 2000
- [c11]Ismet Bayraktaroglu, Alex Orailoglu:
Accumulation-based concurrent fault detection for linear digital state variable systems. Asian Test Symposium 2000: 484- - [c10]Ismet Bayraktaroglu, Alex Orailoglu:
Improved fault diagnosis in scan-based BIST via superposition. DAC 2000: 55-58 - [c9]Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu:
Test Synthesis for Mixed-Signal SOC Paths. DATE 2000: 128-133 - [c8]Ismet Bayraktaroglu, Alex Orailoglu:
Low cost concurrent test implementation for linear digital systems. ETW 2000: 140-143 - [c7]Ismet Bayraktaroglu, Alex Orailoglu:
Cost effective digital filter design for concurrent test. ICASSP 2000: 3323-3326 - [c6]Ismet Bayraktaroglu, Alex Orailoglu:
Unifying methodologies for high fault coverage concurrent and off-line test of digital filters. ISCAS 2000: 705-708 - [c5]Ismet Bayraktaroglu, Alex Orailoglu:
Deterministic partitioning techniques for fault diagnosis in scan-based BIST. ITC 2000: 273-282 - [c4]Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu:
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. VTS 2000: 459-464
1990 – 1999
- 1999
- [j1]Ismet Bayraktaroglu, Arif Selçuk Ögrenci, Günhan Dündar, Sina Balkir, Ethem Alpaydin:
ANNSyS: an Analog Neural Network Synthesis System. Neural Networks 12(2): 325-338 (1999) - [c3]Ismet Bayraktaroglu, Alex Orailoglu:
Low-Cost On-Line Test for Digital Filters. VTS 1999: 446-451 - 1998
- [c2]Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs. Asian Test Symposium 1998: 440- - 1997
- [c1]Ismet Bayraktaroglu, Arif Selçuk Ögrenci, Günhan Dündar, Sina Balkir, Ethem Alpaydin:
ANNSyS (an analog neural network synthesis system). ICNN 1997: 910-915
Coauthor Index
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