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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 2
Volume 2, Number 1, March 1994
- Daniel Audet, Yvon Savaria, N. Arel:
Pipelining communications in large VLSI/ULSI systems. 1-10 - Catherine H. Gebotys:
An optimization approach to the synthesis of multichip architectures. 11-20 - Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King:
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. 21-32 - Neil J. Howard
, Andrew M. Tyrrell, Nigel M. Allinson:
The yield enhancement of field-programmable gate arrays. 115-123 - Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, John C. Curlander:
VLSI systolic binary tree-searched vector quantizer for image compression. 33-44 - Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel:
Block-oriented programmable design with switching network interconnect. 45-53 - Joydeep Ghosh, Anujan Varma, Naveen Krishnamurthy:
Distributed control schemes for fast arbitration in large crossbar networks. 54-67 - Steve C.-Y. Huang, Wayne H. Wolf:
Performance-driven synthesis in controller-datapath systems. 68-80 - Lih-Gwo Jeng, Liang-Gee Chen:
Rate-optimal DSP synthesis by pipeline and minimum unfolding. 81-88 - Vojin G. Oklobdzija:
An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. 124-128 - Sungho Kang, Stephen A. Szygenda:
The simulation automation system (SAS); concepts, implementation, and results. 89-99 - Brian S. Cherkauer, Eby G. Friedman:
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. 100-114 - Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang:
A Gaussian synapse circuit for analog VLSI neural networks. 129-133
Volume 2, Number 2, June 1994
- Jason Cong, Yuzheng Ding:
On area/depth trade-off in LUT-based FPGA technology mapping. 137-148 - Tassos Markas, Mark Royals, Nick Kanopoulos:
Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. 149-156 - Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza:
ALADIN: a multilevel testability analyzer for VLSI system design. 157-171 - Andrew Seawright, Forrest Brewer:
Clairvoyant: a synthesis system for production-based specification. 172-185 - Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee:
RSYN: a system for automated synthesis of reliable multilevel circuits. 186-195 - S. C. Leung, Hon Fung Li:
A syntax-directed translation for the synthesis of delay-insensitive circuits. 196-210 - Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone:
Optimal and heuristic algorithms for solving the binding problem. 211-225 - Lishing Liu:
Partial address directory for cache access. 226-240 - Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS logic testing. 241-248 - Israel Koren, Zahava Koren, Charles H. Stapper:
A statistical study of defect maps of large area VLSI IC's. 249-256 - Choong Gun Oh, Hee Yong Youn:
On concurrent error location and correction of FFT networks. 257-260 - Razak Hossain, Leszek D. Wronski, Alexander Albicki:
Low power design using double edge triggered flip-flops. 261-265 - Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia:
Algorithms and bounds for layer assignment of MCM routing. 265-270
Volume 2, Number 3, September 1994
- Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis:
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. 343-353 - Chien-In Henry Chen, Joel T. Yuen:
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. 273-291 - Hong-Shin Jun, Sun-Young Hwang:
Design of a pipelined datapath synthesis system for digital signal processing. 292-303 - Alex Orailoglu, Ramesh Karri:
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. 304-311 - Ming-Bo Lin, A. Yavuz Oruç:
A fault-tolerant permutation network modulo arithmetic processor. 312-319 - Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj:
Logic design error diagnosis and correction. 320-332 - Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified timing verification and the transition delay of a logic circuit. 333-342 - R. V. Pelletier, Robert D. McLeod:
Loop based design for wafer scale systems. 354-357 - Chang N. Zhang, J. H. Weston, Y.-F. Yan:
Determining objective functions in systolic array designs. 357-360 - K. Tsang, Belle W. Y. Wei:
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer. 360-364 - Barry S. Fagin, C. Renard:
Field programmable gate arrays and floating point arithmetic. 365-367 - Jacob Savir, Srinivas Patil:
On broad-side delay test. 368-372 - Alexandre Yakovlev, A. Petrov, Luciano Lavagno:
A low latency asynchronous arbitration circuit. 372-377 - Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Power-delay characteristics of CMOS adders. 377-381
Volume 2, Number 4, December 1994
- Lars Skovby Nielsen, Cees Niessen, Jens Sparsø, Kees van Berkel:
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. 391-397 - William C. Athas, Lars J. Svensson, Jefferey G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou:
Low-power digital systems based on adiabatic-switching principles. 398-407 - Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. 408-425 - Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. 426-436 - Vivek Tiwari, Sharad Malik, Andrew Wolfe:
Power analysis of embedded software: a first step towards software power minimization. 437-445 - Farid N. Najm:
A survey of power estimation techniques in VLSI circuits. 446-455 - Samit Chaudhuri, Robert A. Walker, J. E. Mitchell:
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. 456-471 - Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi:
A C-testable carry-free divider. 472-488 - Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz:
Fuzzy logic approach to VLSI placement. 489-501 - Kaushik Roy, Sudip Nag:
Automatic synthesis of FPGA channel architecture for routability and performance. 508-511 - Sandip Kundu:
Diagnosing scan chain faults. 512-516 - Charles E. Stroud:
Reliability of majority voting based VLSI fault-tolerant circuits. 516-521 - Raj S. Katti:
A modified Booth algorithm for high radix fixed-point multiplication. 522-524 - Chaitali Chakrabarti, Li-Yu Wang:
Novel sorting network-based architectures for rank order filters. 502-507
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