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ORCID22nd ASP-DAC 2017: Chiba, Japan
- 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017. IEEE 2017, ISBN 978-1-5090-1558-0
- Subhasish Mitra, Deming Chen:
ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations. 1 - K. T. Tim Cheng:
ASP-DAC 2017 keynote speech I-1: Heterogeneous integration of X-tronics: Design automation and education. 2 - John Rogers:
ASP-DAC 2017 keynote speech I-2: Electronics for the human body. 3 - Hiroto Yasuura:
ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. 4 - Korkut Kaan Tokgoz
, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
W-band ultra-high data-rate 65nm CMOS wireless transceiver. 5-6 - Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura:
An image sensor/processor 3D stacked module featuring ThruChip interfaces. 7-8 - Hye-Yeon Yoon, Gwang-Ho Lee, Tae-Hwan Kim:
A 686Mbps 1.85mm2 near-optimal symbol detector for spatial modulation MIMO systems in 0.18μm CMOS. 9-10 - Kei Ikeda, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu:
A scalable time-domain biosensor array using logarithmic cyclic time-attenuation-based TDC for high-resolution and large-scale bio-imaging. 11-12 - Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. 13-14 - Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta:
A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. 15-16 - Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta:
Non-binary cyclic ADC with correlated level shifting technique. 17-18 - Kohei Gamo, Kazuo Nakazato, Kiichi Niitsu:
A current-integration-based CMOS amperometric sensor with 1.2 μm × 2.05 μm electroless-plated microelectrode array for high-sensitivity bacteria counting. 19-20 - Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. 21-22 - Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. 23-24 - Atsuki Kobayashi, Kei Ikeda, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato, Kiichi Niitsu:
Design of an energy-autonomous bio-sensing system using a biofuel cell and 0.19V 53μW integrated supply-sensing sensor with a supply-insensitive temperature sensor and inductive-coupling transmitter. 25-26 - Keita Yogosawa, Hideki Shinohara, Kousuke Miyaji:
A 13.56MHz CMOS active diode full-wave rectifier achieving ZVS with voltage-time-conversion delay-locked loop for wireless power transmission. 27-28 - Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. 29-30 - Lin Cheng, Wing-Hung Ki, Tak-Sang Yim:
A 13.56 MHz on/off delay-compensated fully-integrated active rectifier for biomedical wireless power transfer systems. 31-32 - Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui:
A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications. 33-34 - Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. 35-36 - Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori:
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. 37-38 - Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata:
An FPGA-compatible PLL-based sensor against fault injection attack. 39-40 - Simon J. Bale, James Alfred Walker, Martin A. Trefzer, Andy M. Tyrrell:
Variability mapping at runtime using the PAnDA multi-reconfigurable architecture. 41-42 - Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu:
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. 43-44 - Biruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco:
AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs. 45-50 - Kuo-Kai Hsieh, Sebastian Siatkowski, Li-C. Wang, Wen Chen, Jayanta Bhadra:
Feature extraction from design documents to enable rule learning for improving assertion coverage. 51-56 - Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler:
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. 57-62 - Nhut-Minh Ho, Elavarasi Manogaran, Weng-Fai Wong, Asha Anoosheh:
Efficient floating point precision tuning for approximate computing. 63-68 - Debjyoti Bhattacharjee, Arvind Easwaran, Anupam Chattopadhyay:
Area-constrained technology mapping for in-memory computing using ReRAM devices. 69-74 - Juan Escobedo, Mingjie Lin:
Tessellating memory space for parallel access. 75-80 - Yoichi Tomioka, Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima:
Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation. 81-86 - Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao:
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. 87-92 - Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Efficient circuit failure probability calculation along product lifetime considering device aging. 93-98 - Kent Gauen, Rohit Rangan, Anup Mohan, Yung-Hsiang Lu, Wei Liu, Alexander C. Berg:
Low-power image recognition challenge. 99-104 - Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li:
CNN-based object detection solutions for embedded heterogeneous multicore SoCs. 105-110 - Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo:
Low-power neuromorphic speech recognition engine with coarse-grain sparsity. 111-114 - Ji Li, Ao Ren, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang:
Towards acceleration of deep convolutional neural networks using stochastic computing. 115-120 - Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Enabling fast preemption via Dual-Kernel support on GPUs. 121-126 - Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini:
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. 127-132 - Ho Hyun Shin, Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim, Eui-Young Chung:
Timing window wiper: A new scheme for reducing refresh power of DRAM. 133-138 - Ye Tian, Qiang Xu, Jason Xue:
On efficient message passing in energy harvesting based distributed system. 139-144 - Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis:
Fast-extract with cube hashing. 145-150 - Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A novel basis for logic rewriting. 151-156 - Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Multi-level logic benchmarks: An exactness study. 157-162 - Yi Wu, Chuyu Shen, Yi Jia, Weikang Qian:
Approximate logic synthesis for FPGA by wire removal and local function change. 163-169 - Kun-Lin Lin, Shao-Yun Fang:
Guiding template-aware routing considering redundant via insertion for directed self-assembly. 170-175 - Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Workload-aware static aging monitoring of timing-critical flip-flops. 176-181 - Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. 182-187 - Sina Asadi, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi:
WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches. 188-193 - Francesco Regazzoni, Ilia Polian:
Securing the hardware of cyber-physical systems. 194-199 - Sujit Rokka Chhetri, Jiang Wan, Mohammad Abdullah Al Faruque:
Cross-domain security of cyber-physical systems. 200-205 - Arvind Easwaran, Anupam Chattopadhyay, Shivam Bhasin:
A systematic security analysis of real-time cyber-physical systems. 206-213 - Katsumi Okuda, Minoru Yoshida, Haruhiko Takeyama, Minoru Nakamura:
Automated generation of dynamic binary translators for instruction set simulation. 214-219 - Omayma Matoussi, Frédéric Pétrot:
Loop aware IR-level annotation framework for performance estimation in native simulation. 220-225 - Tim Schmidt, Guantao Liu, Rainer Dömer:
Hybrid analysis of SystemC models for fast and accurate parallel simulation. 226-231 - Michele Lora, Enrico Fraccaroli, Franco Fummi:
Virtual prototyping of smart systems through automatic abstraction and mixed-signal scheduling. 232-237 - Cunxi Yu, Maciej J. Ciesielski:
Efficient parallel verification of Galois field multipliers. 238-243 - Jan Malburg, Tino Flenker, Görschwin Fey:
Property mining using dynamic dependency graphs. 244-250 - Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. 251-256 - John Adler, Ryan Berryhill, Andreas G. Veneris:
An extensible perceptron framework for revision RTL debug automation. 257-262 - Youngchan Kim, Taewhan Kim:
Algorithm for synthesis and exploration of clock spines. 263-268 - Yu-Min Lee, Chi-Han Lee, Yan-Cheng Zhu:
Yield-driven redundant power bump assignment for power network robustness. 269-274 - Meng Liu, Matthias Becker, Moris Behnam, Thomas Nolte:
A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCs. 275-282 - Zhongming Chen, Kim Batselier, Haotian Liu, Ngai Wong:
An efficient homotopy-based Poincaré-Lindstedt method for the periodic steady-state analysis of nonlinear autonomous oscillators. 283-288 - Napoleon Torres-Martinez:
ASP-DAC 2017 keynote speech II: Emerging medical technologies for interfacing the brain: From deep brain stimulation to brain computer interfaces. 289 - Jun Ohta:
Smart electrode - toward a retinal stimulator with the large number of electrodes. 290 - Gregg J. Suaning:
Strategic circuits for neuromodulation of the visual system. 291-294 - Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw:
Design considerations and clinical applications of closed-loop neural disorder control SoCs. 295-298 - Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez:
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. 299 - Marta Ortín-Obón, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi:
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings. 300-305 - Dharanidhar Dang, Sai Vineel Reddy Chittamuru, Rabi N. Mahapatra, Sudeep Pasricha:
Islands of heaters: A novel thermal management framework for photonic NoCs. 306-311 - Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. 312-317 - Caiwen Ding, Ji Li, Weiwei Zheng, Naehyuck Chang, Xue Lin, Yanzhi Wang:
Algorithm accelerations for luminescent solar concentrator-enhanced reconfigurable onboard photovoltaic system. 318-323 - Zuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Yingnan Cui:
Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics. 324-329 - Joshua Marxen, Alex Orailoglu:
Ensuring system security through proximity based authentication. 330-335 - Md Tanvir Arafin, Mingze Gao, Gang Qu:
VOLtA: Voltage over-scaling based lightweight authentication for IoT applications. 336-341 - Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Security analysis of Anti-SAT. 342-347 - Yang You, Jie Gu:
Exploiting accelerated aging effect for on-line configurability and hardware tracking. 348-353 - Dimitrios Tychalas, Nektarios Georgios Tsoutsos, Michail Maniatakos:
SGXCrypter: IP protection for portable executables using Intel's SGX technology. 354-359 - Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. 360-365 - Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An efficient algorithm for stencil planning and optimization in E-beam lithography. 366-371 - Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow:
Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers. 372-377 - Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak:
Optimizing DSA-MP decomposition and redundant via insertion with dummy vias. 378-383 - Naveen Katam, Alireza Shafaei, Massoud Pedram:
Design of multiple fanout clock distribution network for rapid single flux quantum technology. 384-389 - Mingze Gao, Qian Wang, Akshaya S. Kankanhalli-Nagendra, Gang Qu:
A novel data format for approximate arithmetic computing. 390-395 - Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. 396-401 - Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li:
ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. 402-407 - Qian Zhang, Ting Wang, Qiang Xu:
On resilient task allocation and scheduling with uncertain quality checkers. 408-413 - Fan Lin, Kwang-Ting Cheng:
An artificial neural network approach for screening test escapes. 414-419 - Ching-Wen Lin, Chung-Ho Chen:
Processor shield for L1 data cache software-based on-line self-testing. 420-425 - Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. 426-431 - Soumya Banerjee, Wenjing Rao:
A local reconfiguration based scalable fault tolerant many-processor array. 432-437 - Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang:
Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits. 438-443 - Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez:
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. 444-449 - Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan:
An effective legalization algorithm for mixed-cell-height standard cells. 450-455 - Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. 456-462 - Archit Gupta, Tianshi Wang, Ahmet Mahmutoglu Gokcen, Jaijeet Roychowdhury:
STEAM: Spline-based tables for efficient and accurate device modelling. 463-468 - Hui Zhang, Bo Wang:
A time domain behavioral model for oscillators considering flicker noise. 469-474 - Tuotian Liao, Lihong Zhang:
Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits. 475-480 - M. Hassan Najafi, David J. Lilja:
High-speed stochastic circuits using synchronous analog pulses. 481-487 - Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong:
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. 488-493 - Lei Yang, Weichen Liu, Nan Guan, Mengquan Li, Peng Chen, Edwin Hsing-Mean Sha:
Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. 494-499 - Sudarshan Sargur, Roman Lysecky:
Non-intrusive dynamic profiler for multicore embedded systems. 500-505 - Xiaokun Yang, Wujie Wen:
Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips. 506-511 - Ching-Wei Hsieh, Zipeng Li, Tsung-Yi Ho:
Piracy prevention of digital microfluidic biochips. 512-517 - Guan-Ruei Lu, Guan-Ming Huang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
On reliability hardening in cyber-physical digital-microfluidic biochips. 518-523 - Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. 524-529 - Andreas Grimmer, Qin Wang, Hailong Yao, Tsung-Yi Ho, Robert Wille:
Close-to-optimal placement and routing for continuous-flow microfluidic biochips. 530-535 - Steve Trimberger:
ASP-DAC 2017 keynote speech III: All-programmable FPGAs: More powerful devices require more powerful tools. 536 - Hussam Amrouch, Jörg Henkel:
Containing guardbands. 537-542 - Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang:
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. 543-548 - Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou:
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. 549-553 - Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi:
CN-SIM: A cycle-accurate full system power delivery noise simulator. 554-559 - Qiao Li, Liang Shi, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Improving LDPC performance via asymmetric sensing level placement on flash memory. 560-565