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ORCIDPaolo Ienne
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- affiliation: Swiss Federal Institute of Technology in Lausanne, Switzerland
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2020 – today
- 2024
[j53]Stefan Nikolic
, Paolo Ienne:
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. ACM Trans. Reconfigurable Technol. Syst. 17(1): 14:1-14:39 (2024)- [c167]Mohamed Shahawy, Canberk Sönmez, Cemalettin Belentepe, Paolo Ienne:
HardCilk: Cilk-like Task Parallelism for FPGAs. FCCM 2024: 140-150 - [c166]Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne:
DynaRapid: From C to FPGA in a Few Seconds. FPGA 2024: 40 - [c165]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA 2024: 44-54 - [i4]Beatriz Borges, Negar Foroutan, Deniz Bayazit, Anna Sotnikova, Syrielle Montariol, Tanya Nazaretzky, Mohammadreza Banaei, Alireza Sakhaeirad, Philippe Servant, Seyed Parsa Neshaei, Jibril Frej, Angelika Romanou, Gail Weiss, Sepideh Mamooler, Zeming Chen, Simin Fan, Silin Gao, Mete Ismayilzada, Debjit Paul, Alexandre Schöpfer, Andrej Janchevski, Anja Tiede, Clarence Linden, Emanuele Troiani, Francesco Salvi, Freya Behrens, Giacomo Orsi, Giovanni Piccioli, Hadrien Sevel, Louis Coulon, Manuela Pineros-Rodriguez, Marin Bonnassies, Pierre Hellich, Puck van Gerwen, Sankalp Gambhir, Solal Pirelli, Thomas Blanchard, Timothée Callens, Toni Abi Aoun, Yannick Calvino Alonso, Yuri Cho, Alberto Silvio Chiappa, Antonio Sclocchi, Étienne Bruno, Florian Hofhammer, Gabriel Pescia, Geovani Rizk, Leello Dadi, Lucas Stoffl, Manoel Horta Ribeiro, Matthieu Bovel, Yueyang Pan, Aleksandra Radenovic, Alexandre Alahi, Alexander Mathis, Anne-Florence Bitbol, Boi Faltings, Cécile Hébert, Devis Tuia, François Maréchal, George Candea, Giuseppe Carleo, Jean-Cédric Chappelier, Nicolas Flammarion, Jean-Marie Fürbringer, Jean-Philippe Pellet, Karl Aberer, Lenka Zdeborová, Marcel Salathé, Martin Jaggi, Martin Rajman, Mathias Payer, Matthieu Wyart, Michael Gastpar, Michele Ceriotti, Ola Svensson, Olivier Lévêque, Paolo Ienne, Rachid Guerraoui, Robert West, Sanidhya Kashyap, Valerio Piazza, Viesturs Simanis, Viktor Kuncak, Volkan Cevher, Philippe Schwaller, Sacha Friedli, Patrick Jermann, Tanja Käser, Antoine Bosselut:
Could ChatGPT get an Engineering Degree? Evaluating Higher Education Vulnerability to AI Assistants. CoRR abs/2408.11841 (2024) - 2023
- [j52]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. 10(3): 15:1-15:35 (2023) - [j51]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 16(4): 54:1-54:27 (2023) - [j50]Paolo Ienne:
Introduction to the Special Section on FPGA 2022. ACM Trans. Reconfigurable Technol. Syst. 16(4): 56:1-56:2 (2023) - [c164]Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA 2023: 39-45 - [c163]Stefan Nikolic, Paolo Ienne:
Regularity Matters: Designing Practical FPGA Switch-Blocks. FPGA 2023: 99-109 - [e6]Paolo Ienne, Zhiru Zhang:
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023. ACM 2023, ISBN 978-1-4503-9417-8 [contents] - [i3]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR abs/2301.01068 (2023) - 2022
- [j49]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j48]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2142-2155 (2022) - [j47]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15(1): 4:1-4:32 (2022) - [j46]Mikhail Asiatici, Paolo Ienne:
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(2): 13:1-13:33 (2022) - [j45]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. 15(4): 37:1-37:33 (2022) - [c162]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FCCM 2022: 1-9 - [c161]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL 2022: 253-261 - [c160]Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic:
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL 2022: 375-383 - [c159]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA 2022: 247-258 - [e5]Michael Adler, Paolo Ienne:
FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022. ACM 2022, ISBN 978-1-4503-9149-8 [contents] - [i2]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR abs/2202.09685 (2022) - 2021
- [j44]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. 93(12): 1405-1417 (2021) - [c158]Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne:
Global Is the New Local: FPGA Architecture at 5nm and Beyond. FPGA 2021: 34-44 - [c157]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FPGA 2021: 226 - [c156]Stefan Nikolic, Paolo Ienne:
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. FPL 2021: 225-233 - [c155]Mikhail Asiatici, Paolo Ienne:
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA 2021: 609-622 - 2020
- [j43]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13(11): 2676-2690 (2020) - [c154]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP 2020: 133-140 - [c153]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA 2020: 1-10 - [c152]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA 2020: 150-160 - [c151]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA 2020: 186-196 - [c150]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c149]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL 2020: 153-161 - [c148]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops 2020: 211-214
2010 – 2019
- 2019
- [j42]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne:
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7: 103938-103947 (2019) - [c147]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Speculative Dataflow Circuits. FPGA 2019: 162-171 - [c146]Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne:
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. FPGA 2019: 188 - [c145]Mikhail Asiatici, Paolo Ienne:
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA 2019: 310-319 - [c144]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL 2019: 31-37 - [c143]Mikhail Asiatici, Paolo Ienne:
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL 2019: 254-262 - [c142]Gabor Csordas, Mikhail Asiatici, Paolo Ienne:
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT 2019: 188-196 - [c141]Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne:
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT 2019: 197-205 - 2018
- [c140]Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. AHS 2018: 74-81 - [c139]Lana Josipovic, Radhika Ghosal, Paolo Ienne:
Dynamically Scheduled High-level Synthesis. FPGA 2018: 127-136 - [c138]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). FPGA 2018: 294 - [c137]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA 2018: 295 - [c136]João Vieira, Nuno Roma, Pedro Tomás, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Exploiting Compute Caches for Memory Bound Vector Operations. SBAC-PAD 2018: 197-200 - [p2]Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne:
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis 2018: 169-188 - 2017
- [j41]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [j40]João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva:
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5: 14600-14615 (2017) - [j39]Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam:
An Accelerator for High Efficient Vision Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 227-240 (2017) - [j38]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [c135]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c134]Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC 2017: 5:1-5:6 - [c133]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - [c132]Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA 2017: 135-140 - [c131]Grace Zgheib, Paolo Ienne:
Evaluating FPGA clusters under wide ranges of design parameters. FPL 2017: 1-8 - [c130]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - 2016
- [j37]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46: 219-220 (2016) - [j36]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65(4): 1006-1009 (2016) - [j35]Paolo Ienne, Jean-Pierre Talpin:
Guest Editorial: Special Issue on Models and Methodologies for System Design. ACM Trans. Embed. Comput. Syst. 15(2): 29:1-29:2 (2016) - [j34]Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi:
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3489-3498 (2016) - [c129]Francesco Regazzoni, Paolo Ienne:
Instruction Set Extensions for secure applications. DATE 2016: 1529-1534 - [c128]Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA 2016: 80-89 - [c127]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c126]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c125]Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. FPL 2016: 1-4 - [c124]Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180 - [c123]Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. FPT 2016: 181-184 - [c122]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c121]Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner:
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. ICCAD 2016: 95 - [c120]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [e4]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j33]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64(2): 329-341 (2015) - [j32]Xavier Jimenez, David Novo, Paolo Ienne:
Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. ACM Trans. Embed. Comput. Syst. 14(2): 28:1-28:22 (2015) - [j31]Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14(2): 33:1-33:23 (2015) - [c119]Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. DATE 2015: 593-596 - [c118]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM 2015: 97 - [c117]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL 2015: 1-8 - [c116]Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8 - [c115]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - [c114]Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. FPT 2015: 80-87 - [c113]Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne:
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference 2015: 259-275 - [c112]Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam:
ShiDianNao: shifting vision processing closer to the sensor. ISCA 2015: 92-104 - [c111]Panagiotis Skrimponis, Georgios Zindros, Ioannis Parnassos, Muhsen Owaida, Nikolaos Bellas, Paolo Ienne:
Exploring Automatically Generated Platforms in High Performance FPGAs. PARCO 2015: 563-570 - [e3]Yunji Chen, Paolo Ienne, Qing Ji:
Advanced Parallel Processing Technologies - 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings. Lecture Notes in Computer Science 9231, Springer 2015, ISBN 978-3-319-23215-7 [contents] - 2014
- [j30]Walid A. Najjar, Paolo Ienne:
Reconfigurable Computing. IEEE Micro 34(1): 4-6 (2014) - [j29]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11(2): 15:1-15:26 (2014) - [j28]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 62-75 (2014) - [c110]Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu:
A low-cost memory interface for high-throughput accelerators. CASES 2014: 11:1-11:10 - [c109]Andrew Becker, David Novo, Paolo Ienne:
SKETCHILOG: Sketching combinational circuits. DATE 2014: 1-4 - [c108]David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor:
Energy efficient MIMO processing: A case study of opportunistic run-time approximations. DATE 2014: 1-6 - [c107]Xavier Jimenez, David Novo, Paolo Ienne:
Wear unleveling: improving NAND flash lifetime by balancing page endurance. FAST 2014: 47-59 - [c106]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - [c105]Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. FPL 2014: 1-8 - [c104]Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne:
Constrained interpolation for guided logic synthesis. ICCAD 2014: 462-469 - 2013
- [j27]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - [c103]Andrew Becker, David Novo, Paolo Ienne:
Automated circuit elaboration from incomplete architectural descriptions. ACSSC 2013: 391-395 - [c102]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne:
Sleuth: Automated Verification of Software Power Analysis Countermeasures. CHES 2013: 293-310 - [c101]David Novo, Sara El Alaoui, Paolo Ienne:
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. DATE 2013: 15-20 - [c100]Xavier Jimenez, David Novo, Paolo Ienne:
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. DATE 2013: 226-229 - [c99]Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. DATE 2013: 410-415 - [c98]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c97]Madhura Purnaprajna, Paolo Ienne:
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM 2013: 53-56 - [c96]Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu:
Elastic CGRAs. FPGA 2013: 171-180 - [c95]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c94]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - [c93]Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. FPT 2013: 120-127 - [c92]