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ORCIDFPGA 2026: Seaside, CA, USA
- Jing Li
, Grace Zgheib:
Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2026, Seaside, CA, USA, February 22-24, 2026. ACM 2026, ISBN 979-8-4007-2079-6
Paper Session I: CAD
- Ezra Thomas, Jing Li, André DeHon:
Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds. 1-11 - Wenhao Lin, Zewen Li, Xinshi Zang, Evangeline F. Y. Young:
RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs. 12-22 - Ollie Cosgrove, Alastair F. Donaldson, John Wickerson:
Finding and Understanding Bugs in FPGA Place-and-Route Engines. 23-33
Poster Session I
- Fatemeh Arkannezhad, Nader Sehatbakhsh:
Attest Like Software: Formally-Verified Software-Programmable Proof of Execution Architecture Using SoC FPGAs. 34 - Bin Xu, Ayan Banerjee, Sandeep K. S. Gupta:
Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures (FPGAs) for Edge and Physical AI. 35 - Jie Lei, Ruofan Jia, J. Andrew Zhang, Hao Zhang:
A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation. 36 - Canberk Sönmez, Mohamed Shahawy, Paolo Ienne:
Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators. 37 - Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Yeonho Jeong, Tao Wei:
Exploring Real-Time Power Electronics Simulation on AMD AIEs. 38 - Sachini Wickramasinghe, Tian Ye, Cauligi S. Raghavendra, Viktor K. Prasanna:
A Model-Hardware Co-design Framework for Robust and Efficient CNN-Based SAR ATR. 39 - Idris Somoye, David Jovel, Lamia Mannan:
OpenPCIe: An Open-Source PCIe Controller. 40 - Eddie Rydell, Reilly McKendrick, Jeffrey Goeders:
CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists. 41 - Endri Taka, Andre Roesti, Joseph Melber, Pranathi Vasireddy, Kristof Denolf, Diana Marculescu:
Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen™ AI NPUs. 42 - Congwu Zhang, Panyu Wang, Yazhou Wang, Bibo Yang, Mingyu Chen, Yungang Bao, Ke Zhang:
Chrono-Fabric: A Decoupled Hierarchical Framework for Cycle-Accurate Coordination in Multi-FPGA Systems. 43
Paper Session II: Machine Learning
- Duc Hoang, Aarush Gupta, Philip C. Harris:
KANELÉ: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation. 44-55 - Dong Liu, Yanxuan Yu:
CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving. 56-66 - Tianchu Ji, Niranjan Balasubramanian, Michael Ferdman, Peter A. Milder:
Enabling Efficient SpMM for Sparse Attention on GEMM-Optimized Hardware with Block Aggregation. 67-78 - Chang Sun, Zhiqiang Que, Thea Aarrestad, Vladimir Loncar, Jennifer Ngadiuba, Wayne Luk, Maria Spiropulu:
HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs. 79-91
Paper Session III: High-Level Synthesis
- Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne:
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. 92-102 - Shun Katsumi, Emmet Murphy, Lana Josipovic:
EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS. 103-113 - Carmine Rizzi, Sebastian Pfeiler, Lana Josipovic:
HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs. 114-125 - YoungSeok Na, Linus Y. Wong, André DeHon, Jing Jane Li:
HiLFS: FPGA-Orchestrated File System for High-Level Synthesis. 126-136
Poster Session II
- Benedict Short, Ian McInerney, John Wickerson:
A High-level Synthesis Toolchain for the Julia Language. 137 - Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown:
Towards Scheduling of Pipelined Dataflow Graphs in MLIR. 138 - Kevin Townsend:
Multi-Port Memory with Bidirectional Ports for FPGAs Using XOR and LVT Methods. 139 - Jebacyril Arockiaraj, Dhruv Parikh, Viktor K. Prasanna:
NysX: An Accurate and Energy-Efficient FPGA Accelerator for Hyperdimensional Graph Classification at the Edge. 140 - Irfan Waheed, Wajahat Riaz, Babar Sohail:
A Cloud-Native FPGA-Accelerated Framework and Methodology for Hardware Verification. 141 - Shijie Liu, Zhenghao Zeng, Han Jiao, Yihua Huang:
HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV. 142 - Nicolas Deloumeau, Tarek Ould-Bachir, David Evans, Andrew Handke, Jamie Sanderson, François Tetreault:
Synchronized CPU-FPGA Tracing for Heterogeneous Platforms. 143 - Tarun Kholay, Anup Ashok Kedilaya, Aman Arora, Jaydeep P. Kulkarni, Lizy K. John:
MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage. 144 - Ruthwik Reddy Sunketa, Aman Arora:
Closing the Loop on FPGA Verification: An Iterative Framework for Maximizing Routing Resource Coverage. 145 - Shashank Obla, Bin Li, James C. Hoe:
Analysis and Optimization of Input-Dependent Stream Processing Pipelines on FPGAs. 146
Paper Session IV: Industry Track
- Rob Rydberg, Madison N. Emas, John Demme, Ana Ibarra, Kara Kagi, Brandon Klouchek, Abhijeet Lawande, Todd Massengill, David J. Powers, Andrew Putnam:
Hyperscale FPGA Engineering Systems at Microsoft. 147-157 - Madison N. Emas, Austin Baylis, Greg Stitt:
Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications. 158-168 - Linh Nguyen, Nguyen Le, Tony-Dat Tran, Jagannath Panduranga Rao, Andrew Putnam:
AI-Assisted Copilot Automation for Reliable FPGA Verification at Hyperscale. 169-178
Poster Session III
- Kaushikkumar S. Rathva, Aakarsh Alam, Srini Srinivasan, Sumit K. Mandal:
FARE: A Fine-grained Pipelined Reconfigurable FlashAttention Kernel. 179 - Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia:
PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros. 180 - Ryo Iwasaki, Tatsuya Sasaki, Yumi Iseki, Sota Kohata, Miyu Yoshida, Kenshu Seto, Masahiro Iida:
Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture. 181 - Dave Ojika, Projjal Gupta, Preethi Budi, Herman Lam, Shreya Mehrotra:
RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines: An Industry Evaluation of Control-Plane Bottlenecks and Sustained Throughput Metrics. 182 - Yang Zou, Zijian Ding, Chi Wang, Yizhou Sun, Jason Cong:
AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow. 183 - Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung, Ray C. C. Cheung, Weitao Xu:
ViM-Q: Energy Efficient Algorithm-Hardware Co-Design for Dynamically Quantized Vision Mamba Models. 184 - John Wohlbier, Daniel Bonness, Jodi Miller, Marika Schubert:
Modulation Recognition in a System-on-Chip. 185 - Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk:
CODESCA: Co-Design for Spectral Clustering Acceleration. 186 - Cheng Chen, Gangqiang Yang, Hongchao Zhou, Hailiang Xiong, Zhiguo Wan:
FlexMSM: A Flexible FPGA-Based Accelerator for Multi-Scalar Multiplication with Reconfigurable Modular Arithmetic and Optimized Pippenger Scheduling. 187 - Doru-Thom Popovici, Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Susanne Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, John Shalf:
A Hierarchical Methodology for Hardware Design Comparison in HPC Workloads. 188
Paper Session V: Architecture
- Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao:
vFPGA: Towards Sub-µs Reconfiguration via 3D FPGA and Packaging Co-Design. 189-200 - Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin:
TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement. 201-211 - Jundong Wu, Zhendong Zheng, Lei Gong, Chao Wang, Xuehai Zhou:
UDP: A Universal DSP Packing Framework for Low-bitwidth MAC Acceleration on FPGAs. 212-223
Paper Session VI: Computing Engines
- Philip Stachura, Xin Wu, Christian Plessl, Zhenman Fang:
SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry. 224-234 - Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng:
Hummingbird+: Advancing FPGA-based LLM Deployment from Research Prototype to Edge Product. 235-246 - Ye Qiao, Zhiheng Chen, Yifan Zhang, Yian Wang, Sitao Huang:
TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs. 247-257 - Farid Chalabi, Guy Lemieux:
Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution. 258-264
Paper Session VII: Applications
- Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna:
HERA: A Bandwidth-efficient Accelerator for Fully Homomorphic Encryption on HBM-enabled FPGA. 265-276 - Greg Stitt, Wesley Piard, Christopher Crary:
EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter. 277-287 - Sheng Lan, Ying Li, Zhongxian Liang, Wenjun Li, Yao Xin, Ying Wan, Hui Li, Weizhe Zhang:
MegaTurbo: A Scalable FPGA-based Engine for MegaFlow Classifier in Open vSwitch. 288-299
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