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Semantic ScholarISCAS 2005: Kobe, Japan - Volume 2
International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. IEEE 2005, ISBN 0-7803-8834-8 Andreas Spanias, Venkatraman Atti:
Rate determination based on perceptual loudness. 848-851Benny Sallberg, Mattias Dahl, Henrik Åkesson, Ingvar Claesson:
A mixed analog-digital hybrid for speech enhancement purposes. 852-855Hai Quang Dam, Sven Nordholm, Hai Huyen Dam, Siow Yong Low:
Adaptive beamformer for hands-free communication system in noisy environments. 856-859Sourabh Ravindran, David V. Anderson:
Audio classification and scene recognition and for hearing aids. 860-863Yu Shao, Chip-Hong Chang:
A versatile speech enhancement system based on perceptual wavelet denoising. 864-867Abhijeet Sangwan, Wei-Ping Zhu, M. Omair Ahmad:
Improved voice activity detection via contextual information and noise suppression. 868-871Hiroshi Fujisaki, Gerhard Keller:
Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chains. 872-875Ji Yao, Anthony J. Lawrance:
Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systems. 876-879Chengqing Li, Xinxiao Li, Shujun Li, Guanrong Chen:
Cryptanalysis of a multistage encryption system. 880-883Yutaka Jitsumatsu, Tohru Kohda:
Design of code-matched receiver for DS/CDMA communications. 884-887Slobodan Kozic, Thomas Schimming:
Coded modulation based on higher dimensional chaotic maps. 888-891Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Long period pseudo random bit generators derived from a discretized chaotic map. 892-895Haiyan Shu, Lap-Pui Chau:
Frame size selection in video downsizing transcoding application. 896-899Deepak P. Nayak, Dipan B. Mehta, Uday B. Desai:
A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcoders. 900-903Viet Anh Nguyen, Yap-Peng Tan:
Efficient video transcoding between H.263 and H.264/AVC standards. 904-907Kai-Tat Fung, Wan-Chi Siu:
Low complexity H.263 to H.264 video transcoding using motion vector decomposition. 908-911Mei Kodama, Shunya Suzuki:
Consideration of transcoding using updatable scalability for selective quality video content delivery method. 912-915Carlos Salazar-Lazaro, Trac D. Tran:
Flexible resizing algorithms for video transcoding. 916-919Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue:
A low-power, 20-Gb/s continuous-time adaptive passive equalizer. 920-923Norbert Neurohr, Matthias Schoebinger, Edoardo Prete, Anthony Sanders:
Adaptive decision-feedback equalization for band-limited high-speed serial links. 924-927Junhua Tian, Bo Shen, Zheng Li, Jianing Su, Qianling Zhang:
Joint carrier recovery and adaptive equalization for high-order QAM. 928-931Miguel A. Melgarejo, Fredy Olarte, Pedro Ladino:
Hardware realization of fuzzy adaptive filters for non linear channel equalization. 932-935Anthony Chan Carusone:
Jitter equalization for binary baseband communication. 936-939Ting-An Lin, Chen-Yi Lee:
Predictive equalizer design for DVB-T system. 940-943Jeong-Hyu Yang, Chang-Su Kim, Sang-Uk Lee:
Progressive coding of 3D dynamic mesh sequences using spatiotemporal decomposition. 944-947Jingliang Peng, Sheng Yang, C.-C. Jay Kuo:
Progressive lossless 3D mesh encoder with octree-based space partitioning. 948-951Hao-Song Kong, Anthony Vetro, Toshihiko Hata, Naoki Kuwahara:
Fast region-of-interest transcoding for JPEG 2000 images. 952-955Jae-Young Sim, Sang-Uk Lee, Chang-Su Kim:
Construction of regular 3D point clouds using octree partitioning and resampling. 956-959Dong Wang, Cedric Nishan Canagarajah, David R. Bull:
Slice group based multiple description video coding with three motion compensation loops. 960-963Peng Wang, Rui Cai, Shi-Qiang Yang:
Improving classification of video shots using information-theoretic co-clustering. 964-967Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
The upper bound of the second-order modes of linear state-space systems [digital filter example]. 968-971Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
A novel property of the second-order modes of discrete-time systems under variable transformation. 972-975Aziz S. Inan, Peter M. Osterberg:
Special singularity integrals encountered in electric circuits [RLC circuit examples]. 976-979Alexei S. Adalev, Nikolai V. Korovkin, Masashi Hayakawa:
Identification of electric circuits: problems and methods of solution accuracy enhancement. 980-983Luis Nero Alves, Rui L. Aguiar:
On the effect of time delays in negative feedback amplifiers. 984-987Svante Signell:
Jittered uniform sampling - examples. 988-991Barbara Cannas, Alessandra Fanni, Augusto Montisci:
Testability evaluation for analog linear circuits via transfer function analysis. 992-995Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch:
Synthesis of MITE log-domain filters with unique operating points. 996-999Soliman A. Mahmoud:
Low voltage high current gain CMOS digitally controlled fully differential CCII [variable gain amplifier application example]. 1000-1003Boonchai Boonchu, Wanlop Surakampontorn:
A new NMOS four-quadrant analog multiplier. 1004-1007Juan M. Carrillo, J. Francisco Duque-Carrillo, Antonio Jesús Torralba Silgado, Ramón González Carvajal:
Class-AB rail-to-rail CMOS analog buffer. 1008-1011Eduardo Rapoport, Fernando Antonio Pinto Barúqui, Antonio Petraglia:
IC design of an analog tunable crossover network. 1012-1015Varakorn Kasemsuwan, Teerawat Arthansiri, Hyung Keun Ahn:
A ± 1.5 V high frequency four quadrant current multiplier. 1016-1019Fábio A. Pereira, Mário C. G. de Oliveira, Ana Isabela Araújo Cunha:
CMOS analog current-mode multiplier based on the advanced compact MOSFET model. 1020-1023T. Yasuda:
On-chip temperature sensor with high tolerance for process and temperature variation. 1024-1027Yaxiong Zhang, Alister Hamilton:
A current mode Palmo cell for programmable analogue signal processing. 1028-1031Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu:
A memory-reduced log-MAP kernel for turbo decoder. 1032-1035Hanho Lee:
An ultra high-speed Reed-Solomon decoder. 1036-1039Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang:
A new low-power turbo decoder using HDA-DHDD stopping iteration. 1040-1043Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli:
Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. 1044-1047Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay:
Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric. 1048-1050Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed:
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems. 1051-1054Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang:
A 12.5 Gbps CMOS input sampler for serial link receiver front end. 1055-1058Zeynep Toprak Deniz, Yusuf Leblebici:
Low-power current mode logic for improved DPA-resistance in embedded systems. 1059-1062Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim:
A new level-up shifter for high speed and wide range interface in ultra deep sub-micron. 1063-1065Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti:
A novel CMOS logic style with data independent power consumption. 1066-1069Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su:
A phase-detect synchronous mirror delay for clock skew-compensation circuits. 1070-1073I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu:
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. 1074-1077Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects. 1078-1081Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam:
A closed-form delay formula for on-chip RLC interconnects in current-mode signaling. 1082-1085Soo-Chang Pei, Meng-Ping Kao:
Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices. 1086-1089Truong T. Nguyen, Soontorn Oraintara:
Multidimensional filter banks design by direct optimization. 1090-1093S. C. Chan, S. S. Yin:
On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banks. 1094-1097Robert Bregovic, Tapio Saramäki:
Design of two-channels FIR filterbanks with rational sampling factors using the FRM technique. 1098-1101Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. 1102-1105Pilar Martín-Martín, Fernando Cruz-Roldán, Tapio Saramäki:
: Optimized transmultiplexers for multirate systems. 1106-1109Truong T. Nguyen, Soontorn Oraintara:
A class of directional filter banks [image processing applications]. 1110-1113Mariane R. Petraglia, Paulo B. Batalheiro:
Filter bank design for an adaptive subband structure with critical sampling using a new adaptation scheme. 1114-1117Hau-Jie Liang, Shuenn-Shyang Wang:
Architectural design of fractal image coder based on kick-out condition. 1118-1121Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal:
Dictionary-based program compression on transport triggered architectures. 1122-1125Bo Fang, Guobin Shen, Shipeng Li, Huifang Chen:
Techniques for efficient DCT/IDCT implementation on generic GPU. 1126-1129Yun Yang, Wenqing Zhao, Yasuaki Inoue:
High-performance systolic arrays for band matrix multiplication. 1130-1133Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen:
Block-level parallel processing for scaling evenly divisible frames. 1134-1137Daewook Kim, Manho Kim, Gerald E. Sobelman:
Parallel FFT computation with a CDMA-based network-on-chip. 1138-1141Hongtu Jiang, Håkan Ardö, Viktor Öwall:
Hardware accelerator design for video segmentation with multi-modal background modelling. 1142-1145Saed Samadi, M. Omair Ahmad, M. N. S. Swamy:
Multiplier-free structures for exact generation of natural powers of integers. 1146-1149Ching-Yuan Yang, Yu Lee:
A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. 1150-1153Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, A. Dabrowski:
3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. 1154-1157Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang:
A 0.18µm CMOS transceiver design for high-speed backplane data communications. 1158-1161Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue:
A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. 1162-1165Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas:
An electrically adjustable distributed pulse shaping filter for 40 Gbit/s optical links. 1166-1169Mona Mostafa Hella, Richard Panock:
Dual-loop control of laser drivers for 3.125GHz optical transceivers. 1170-1173Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. 1174-1177Vasanth Kakani, Foster F. Dai, Richard C. Jaeger:
An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. 1178-1181Kun-Hsien Lin, Ming-Dou Ker:
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. 1182-1185Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu:
A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump. 1190-1193Markus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ:
ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. 1194-1197Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong:
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. 1198-1201Elyse Rosenbaum, Sami Hyvonen:
On-chip ESD protection for RF I/Os: devices, circuits and models. 1202-1205Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
A methodology for partitioning DSP applications in hybrid reconfigurable systems. 1206-1209Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations. 1210-1213Minoru Watanabe, Fuminori Kobayashi:
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. 1214-1217Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen:
Pipelining technique for energy-aware datapaths. 1218-1221Somsubhra Mondal, Seda Ogrenci Memik:
A low power FPGA routing architecture. 1222-1225Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan:
Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]. 1226-1229Zhi Zhou, Shijun Sun, Shawmin Lei, Ming-Ting Sun:
Motion information and coding mode reuse for MPEG-2 to H.264 transcoding. 1230-1233Yeping Su, Jun Xin, Anthony Vetro, Huifang Sun:
Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domain. 1234-1237You-Neng Xiao, Hong Lu, Xiangyang Xue, Viet Anh Nguyen, Yap-Peng Tan:
Efficient rate control for MPEG-2 to H.264/AVC transcoding. 1238-1241Chen-Po Chang, Chia-Wen Lin:
R-D optimized quantization of H.264 SP-frames for bitstream switching under storage constraints. 1242-1245Xiaoan Lu, Alexis Michael Tourapis, Peng Yin, Jill M. Boyce:
Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcoding. 1246-1249Ching-Yung Lin, Belle L. Tseng:
Optimizing user expectations for video semantic filtering and abstraction. 1250-1253Lacina M. Coulibaly, H. J. Kadim:
Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation. 1254-1257Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang:
An all-digital pulsewidth control loop. 1258-1261Hui Zhang, Pinaki Mazumder:
Design of a new sense amplifier flip-flop with improved power-delay-product. 1262-1265Davide Baderna, Alessandro Cabrini, Guido De Sandre, Francesco De Santis, Marco Pasotti, Andrea Rossini, Guido Torelli:
A 1.2 V sense amplifier for high-performance embeddable NOR flash memories. 1266-1269Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Casagrande, Roberto Gastaldi, Claudio Resta, Guido Torelli, Daniele Zella:
SET and RESET pulse characterization in BJT-selected phase-change memories. 1270-1273Jing Chen, Miao Li, Tad A. Kwasniewski:
Decision feedback equalization for high-speed backplane data communications. 1274-1277Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai:
Interconnect model reductions by using the AORA algorithm with considering the adjoint network. 1278-1281Hua Tang, Alex Doboli:
Parameter domain pruning for improving convergence of synthesis algorithms. 1282-1285Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli:
Enriching an analog platform for analog-to-digital converter design. 1286-1289Alfred Tze-Mun Leung, Roni Khazaka:
Parametric model order reduction technique for design optimization. 1290-1293Gülin Tulunay, Sina Balkir:
Design automation of single-ended LNAs using symbolic analysis. 1294-1297Trent McConaghy, Georges G. E. Gielen:
Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. 1298-1301Vahid Yousefzadeh, Eduard Alarcón, Dragan Maksimovic:
Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers. 1302-1305Shiyan Hu, Han Huang, Dariusz Czarkowski:
Hybrid trigonometric differential evolution for optimizing harmonic distribution. 1306-1309Boris Axelrod, Yefim Berkovich, Adrian Ioinovici:
Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode. 1310-1313Yushan Li, Dragan Maksimovic:
High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers. 1314-1317Carlos Meza, Domingo Biel, Luis Martinez-Salamero, Francisco Guinjoan:
Boost-buck inverter variable structure control for grid-connected photovoltaic systems. 1318-1321Hirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori:
Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses. 1322-1325Jingbo Yang, Meng Tong Tan, Joseph Sylvester Chang:
Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation. 1326-1329Joachim Neves Rodrigues, Thomas Olsson, Leif Sörnmo, Viktor Öwall:
A dual-mode wavelet based R-wave detector using single-Vt for leakage reduction [cardiac pacemaker applications]. 1330-1333Hakan Gürkan, Ümit Güz, B. Siddik Yarman:
An efficient ECG data compression technique based on predefined signature and envelope vector banks. 1334-1337Qiyue Zou, Zhiping Lin, Raimund J. Ober:
The CRLB for bilinear systems and its biomedical applications. 1338-1341Kyle E. Thomson, Theo Shlien, Yasir Suhail, Karim G. Oweiss:
Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices. 1342-1345Yehya H. Ghallab, Wael M. Badawy:
A novel CMOS lab-on-a-chip for biomedical applications. 1346-1349Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu:
Probabilistic congestion prediction in hierarchical quad-grid model. 1350-1353Akira Matsubayashi:
Small congestion embedding of separable graphs into grids of the same size. 1354-1357Toshinori Yamada, Hiroyuki Kawakita, Tadashi Nishiyama, Shuichi Ueno:
On VLSI decompositions for d-ary de Bruijn graphs (extended abstract). 1358-1361Makoto Fujimoto, Daisuke Takafuji, Toshimasa Watanabe:
Approximation algorithms for the rectilinear Steiner tree problem with obstacles. 1362-1365Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen:
Wiring area optimization in floorplan-aware hierarchical power grids. 1366-1369Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee:
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. 1370-1373Jen-Lin Fan, Jieh-Tsorng Wu:
A robust background calibration technique for switched-capacitor pipelined ADCs. 1374-1377Le Jin, Degang Chen, Randall L. Geiger:
A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals. 1378-1381Ding-Lan Shen, Tai-Cheng Lee:
A linear-approximation technique for digitally-calibrated pipelined A/D converters. 1382-1385Cristiano Azzolini, Andrea Boni, Alessio Facen, Matteo Parenti, Davide Vecchi:
Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology. 1386-1389