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ORCIDWalid A. Najjar
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- affiliation: University of California, Riverside, CA, USA
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2020 – today
- 2021
[j42]Jose M. Rodriguez Borbon
, Junjie Huang, Bryan M. Wong, Walid A. Najjar:
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs. ACM Trans. Archit. Code Optim. 18(3): 27:1-27:25 (2021)- [j41]Bashar Romanous, Skyler Windh, Ildar Absalyamov, Prerna Budhkar, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras:
Efficient local locking for massively multithreaded in-memory hash-based operators. VLDB J. 30(3): 333-359 (2021) - 2020
- [j40]Jose M. Rodriguez Borbon, Xiaoyin Ma, Amit K. Roy-Chowdhury, Walid A. Najjar:
Heterogeneous Acceleration of HAR Applications. IEEE Trans. Circuits Syst. Video Technol. 30(3): 888-902 (2020) - [c97]Bashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar:
High-Performance Parallel Radix Sort on FPGA. FCCM 2020: 224
2010 – 2019
- 2019
- [j39]Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar:
Efficient Main-Memory Top-K Selection For Multicore Architectures. Proc. VLDB Endow. 13(2): 114-127 (2019) - [j38]Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras:
Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads. ACM Trans. Archit. Code Optim. 16(2): 13:1-13:28 (2019) - [j37]Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar:
PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs. ACM Trans. Model. Comput. Simul. 29(2): 12:1-12:25 (2019) - [c96]Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar:
GPU Accelerated Top-K Selection With Efficient Early Stopping. ADMS@VLDB 2019: 10-21 - 2018
- [c95]Vasileios Zois, Divya Gupta, Vassilis J. Tsotras, Walid A. Najjar, Jean-François Roy:
Massively parallel skyline computation for processing-in-memory architectures. PACT 2018: 1:1-1:12 - 2017
- [c94]Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar:
PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs. SIGSIM-PADS 2017: 133-144 - 2016
- [c93]Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras:
FPGA-accelerated group-by aggregation using synchronizing caches. DaMoN 2016: 11:1-11:9 - [c92]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c91]Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury:
Optimizing hardware design for Human Action Recognition. FPL 2016: 1-11 - [p2]Walid A. Najjar, Jason R. Villarreal, Robert J. Halstead:
ROCCC 2.0. FPGAs for Software Programmers 2016: 191-204 - [e6]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - [e5]Walid A. Najjar, Andreas Gerstlauer:
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016. IEEE 2016, ISBN 978-1-5090-3076-7 [contents] - 2015
- [j36]Roger Moussalli, Ildar Absalyamov, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras:
High performance FPGA and GPU complex pattern matching over spatio-temporal streams. GeoInformatica 19(2): 405-434 (2015) - [j35]Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Zabdiel Luna, Omar Hussaini, Walid A. Najjar:
High-Level Language Tools for Reconfigurable Computing. Proc. IEEE 103(3): 390-408 (2015) - [j34]Edward B. Fernandez, Jason R. Villarreal, Stefano Lonardi, Walid A. Najjar:
FHAST: FPGA-Based Acceleration of Bowtie in Hardware. IEEE ACM Trans. Comput. Biol. Bioinform. 12(5): 973-981 (2015) - [j33]Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury:
Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs. IEEE Trans. Circuits Syst. Video Technol. 25(6): 1051-1062 (2015) - [c90]Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar, Vassilis J. Tsotras:
FPGA-based Multithreading for In-Memory Hash Joins. CIDR 2015 - [c89]Skyler Windh, Prerna Budhkar, Walid A. Najjar:
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. ICCAD 2015: 331-336 - 2014
- [j32]Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar:
Compiling irregular applications for reconfigurable systems. Int. J. High Perform. Comput. Netw. 7(4): 258-268 (2014) - [j31]Walid A. Najjar, Paolo Ienne:
Reconfigurable Computing. IEEE Micro 34(1): 4-6 (2014) - [j30]Roger Moussalli, Mariam Salloum, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras:
A study on parallelizing XML path filtering using accelerators. ACM Trans. Embed. Comput. Syst. 13(4): 93:1-93:28 (2014) - [c88]Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury:
High-Throughput Fixed-Point Object Detection on FPGAs. FCCM 2014: 107 - 2013
- [c87]Xi Luo, Walid A. Najjar, Vagelis Hristidis:
Efficient near-duplicate document detection using FPGAs. IEEE BigData 2013: 54-61 - [c86]Robert J. Halstead, Walid A. Najjar:
Compiled multithreaded data paths on FPGAs for dynamic workloads. CASES 2013: 3:1-3:10 - [c85]Walid A. Najjar, Jason R. Villarreal:
FPGA code accelerators - the compiler perspective. DAC 2013: 141:1-141:6 - [c84]Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan:
A High Throughput No-Stall Golomb-Rice Hardware Decoder. FCCM 2013: 65-72 - [c83]Roger Moussalli, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras:
Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying. SSTD 2013: 201-222 - [c82]Ildar Absalyamov, Roger Moussalli, Vassilis J. Tsotras, Walid A. Najjar:
High-Performance XML Twig Filtering using GPUs. ADMS@VLDB 2013: 13-24 - 2012
- [c81]Edward Fernandez, Walid A. Najjar, Stefano Lonardi, Jason R. Villarreal:
Multithreaded FPGA acceleration of DNA sequence mapping. HPEC 2012: 1-6 - 2011
- [c80]Edward Fernandez, Walid A. Najjar, Stefano Lonardi:
String Matching in Hardware Using the FM-Index. FCCM 2011: 218-225 - [c79]Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Massively parallel XML twig filtering using dynamic programming on FPGAs. ICDE 2011: 948-959 - [c78]Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar:
Exploring irregular memory accesses on FPGAs. IA3@SC 2011: 31-34 - [c77]Roger Moussalli, Robert J. Halstead, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Efficient XML Path Filtering Using GPUs. ADMS@VLDB 2011: 9-18 - 2010
- [j29]Betul Buyukkurt, John Cortes, Jason R. Villarreal, Walid A. Najjar:
Impact of high-level transformations within the ROCCC framework. ACM Trans. Archit. Code Optim. 7(4): 17:1-17:36 (2010) - [c76]Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert J. Halstead:
Designing Modular Hardware Accelerators in C with ROCCC 2.0. FCCM 2010: 127-134 - [c75]Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi:
Exploration of Short Reads Genome Mapping in Hardware. FPL 2010: 360-363 - [c74]Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Accelerating XML Query Matching through Custom Stack Generation on FPGAs. HiPEAC 2010: 141-155 - [c73]Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamonn J. Keogh, Vit Niennattrakul:
Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs. ICDM 2010: 1001-1006
2000 – 2009
- 2009
- [j28]Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar:
Tunable and Energy Efficient Bus Encoding Techniques. IEEE Trans. Computers 58(8): 1049-1062 (2009) - [j27]Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar:
Energy-efficient encoding techniques for off-chip data buses. ACM Trans. Embed. Comput. Syst. 8(2): 9:1-9:23 (2009) - [c72]Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Vassilis J. Tsotras, Walid A. Najjar:
Boosting XML filtering through a scalable FPGA-based architecture. CIDR 2009 - [c71]Walid A. Najjar, Jason R. Villarreal:
Reconfigurable Computing in the New Age of Parallelism. SAMOS 2009: 255-262 - [e4]Walid A. Najjar, Michael J. Schulte:
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, July 20-23, 2009. IEEE 2009, ISBN 978-1-4244-4501-1 [contents] - [i2]Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Walid A. Najjar, Vassilis J. Tsotras:
Boosting XML Filtering with a Scalable FPGA-based Architecture. CoRR abs/0909.1781 (2009) - 2008
- [j26]Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar:
A Compiler Intermediate Representation for Reconfigurable Fabrics. Int. J. Parallel Program. 36(5): 493-520 (2008) - [j25]Michael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov:
OpenFPGA CoreLib core library interoperability effort. Parallel Comput. 34(4-5): 231-244 (2008) - [j24]Zhi Guo, Walid A. Najjar, Betul Buyukkurt:
Efficient hardware code generation for FPGAs. ACM Trans. Archit. Code Optim. 5(1): 6:1-6:26 (2008) - [c70]Betul Buyukkurt, Walid A. Najjar:
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. FPL 2008: 655-658 - [c69]Jason R. Villarreal, Walid A. Najjar:
Compiled hardware acceleration of Molecular Dynamics code. FPL 2008: 667-670 - [e3]Walid A. Najjar, Holger Blume:
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2008), Samos, Greece, July 21-24, 2008. IEEE 2008, ISBN 978-1-4244-1985-2 [contents] - 2007
- [c68]Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan:
Compiling PCRE to FPGA for accelerating SNORT IDS. ANCS 2007: 127-136 - [c67]Walid A. Najjar:
Compiling code accelerators for FPGAs. CASES 2007: 1-2 - [c66]Walid A. Najjar:
Compiling code accelerators for FPGAs. CODES+ISSS 2007: 2 - [c65]Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760 - [c64]Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid:
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. FPL 2007: 533-536 - [e2]Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis:
FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007. IEEE 2007, ISBN 1-4244-1060-6 [contents] - [i1]Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs. CoRR abs/0710.4716 (2007) - 2006
- [j23]Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi:
Compile-time area estimation for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 11(1): 104-122 (2006) - [j22]Song Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar:
Efficient indexing data structures for flash-based sensor devices. ACM Trans. Storage 2(4): 468-503 (2006) - [c63]Betul Buyukkurt, Zhi Guo, Walid A. Najjar:
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. ARC 2006: 401-412 - [c62]Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar:
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. ARC 2006: 413-418 - [c61]Zhi Guo, Abhishek Mitra, Walid A. Najjar:
Automation of IP Core Interface Generation for Reconfigurable Computing. FPL 2006: 1-6 - [c60]Zhi Guo, Walid A. Najjar:
A Compiler Intermediate Representation for Reconfigurable Fabrics. FPL 2006: 1-4 - [c59]Greg Stitt, Frank Vahid, Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C. ICCAD 2006: 716-723 - [c58]Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar:
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. ICCD 2006: 127-133 - 2005
- [j21]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A way-halting cache for low-energy high-performance systems. ACM Trans. Archit. Code Optim. 2(1): 34-54 (2005) - [j20]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
A highly configurable cache for low energy embedded systems. ACM Trans. Embed. Comput. Syst. 4(2): 363-387 (2005) - [c57]Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs. DATE 2005: 112-117 - [c56]Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar:
MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. FAST 2005 - [c55]Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure. FPGA 2005: 118-124 - [c54]Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang:
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. ICCD 2005: 631-633 - [c53]Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar:
Data Acquisition in Sensor Networks with Large Memories. ICDE Workshops 2005: 1188 - [c52]Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar:
A tunable bus encoder for off-chip data buses. ISLPED 2005: 319-322 - [c51]Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Anirban Mitra, Anirban Banerjee, Walid A. Najjar:
Towards In-Situ Data Storage in Sensor Databases. Panhellenic Conference on Informatics 2005: 36-46 - [c50]Dinesh C. Suresh, Walid A. Najjar, Jun Yang:
Power Efficient Instruction Caches for Embedded Systems. SAMOS 2005: 182-191 - [c49]Anirban Banerjee, Abhishek Mitra, Walid A. Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos:
RISE - Co-S : high performance sensor storage and Co-processing architecture. SECON 2005: 1-12 - [c48]Anirban Banerjee, Anirban Mitra, Walid A. Najjar:
Splitting the sensor node. SenSys 2005: 270-271 - [e1]Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar:
Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005. ACM 2005, ISBN 1-59593-149-X [contents] - 2004
- [c47]Walid A. Najjar:
From Here to Main-stream: The Present and Future of Reconfigurable Computing. ERSA 2004: 17 - [c46]Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors. FPGA 2004: 162-170 - [c45]Walid A. Najjar:
"How Long is Your Belt?" Towards a Single Device for Multiple Functions. ICPS 2004: 19 - [c44]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A way-halting cache for low-energy high-performance systems. ISLPED 2004: 126-131 - [c43]Zhi Guo, Betul Buyukkurt, Walid A. Najjar:
Input data reuse in compiling window operations onto reconfigurable hardware. LCTES 2004: 249-256 - 2003
- [j19]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Comput. Archit. Lett. 2 (2003) - [j18]Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross:
High-Level Language Abstraction for Reconfigurable Computing. Computer 36(8): 63-69 (2003) - [j17]Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes:
Automatic compilation to a coarse-grained reconfigurable system-opn-chip. ACM Trans. Embed. Comput. Syst. 2(4): 560-589 (2003) - [c42]Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan:
Power efficient encoding techniques for off-chip data buses. CASES 2003: 267-275 - [c41]Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh:
First results with eBlocks: embedded systems building blocks. CODES+ISSS 2003: 168-175 - [c40]Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar:
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. HiPC 2003: 44-54 - [c39]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
A Highly-Configurable Cache Architecture for Embedded Systems. ISCA 2003: 136-146 - [c38]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
Energy Benefits of a Configurable Line Size Cache for Embedded Systems. ISVLSI 2003: 87-91 - [c37]Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt:
Profiling tools for hardware/software partitioning of embedded applications. LCTES 2003: 189-198 - 2002
- [j16]Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar:
Improving Software Performance with Configurable Logic. Des. Autom. Embed. Syst. 7(4): 325-339 (2002) - [j15]A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar:
Mapping a Single Assignment Programming Language to Reconfigurable Systems. J. Supercomput. 21(2): 117-130 (2002) - [c36]Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi:
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. FCCM 2002: 239- - [c35]A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar:
Compiling ATR Probing Codes for Execution on FPGA Hardware. FCCM 2002: 301-302 - 2001
- [j14]Lucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar:
Resource Management in Dataflow-Based Multithreaded Execution. J. Parallel Distributed Comput. 61(5): 581-608 (2001) - [j13]Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani:
A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. IEEE Trans. Computers 50(7): 647-659 (2001) - [j12]Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm:
An automated process for compiling dataflow graphs into reconfigurable hardware. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 130-139 (2001) - [c34]Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm:
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. CASES 2001: 116-125 - [c33]Jean-Luc Gaudiot, Thomas DeBoni, John Feo, A. P. Wim Böhm, Walid A. Najjar, Patrick Miller:
The Sisal Project: Real World Functional Programming. Compiler Optimizations for Scalable Parallel Systems Languages 2001: 45-72 - [c32]A. P. Wim Böhm, Bruce A. Draper, Walid A. Najjar, Jeffrey Hammes, Robert Rinker, Monica Chawathe, Charlie Ross:
One-Step Compilation of Image Processing Applications to FPGAs. FCCM 2001: 209-218 - [c31]Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins:
Compiling SA-C Programs to FPGAs: Performance Results. ICVS 2001: 220-235 - [c30]Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar:
Loop fusion and temporal common subexpression elimination in window-based loops. IPDPS 2001: 142 - [c29]Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani:
Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes. IPDPS 2001: 160 - 2000
- [c28]Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper:
Compiling Image Processing Applications to Reconfigurable Hardware. ASAP 2000: 56-65 - [c27]Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins:
Compiling and Optimizing Image Processing Algorithms for FPGAs. CAMP 2000: 222-231 - [c26]Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper:
A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. PDPTA 2000
1990 – 1999
- 1999
- [j11]Walid A. Najjar, Edward A. Lee, Guang R. Gao:
Advances in the dataflow computational model. Parallel Comput. 25(13-14): 1907-1929 (1999) - [c25]