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ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 17
Volume 17, Number 1, March 2024
- Anupreetham Anupreetham
, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-Sun Seo:
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. 1:1-1:20 - Zimeng Fan, Wei Hu, Fang Liu, Dian Xu, Hong Guo, Yanxiang He, Min Peng:
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices. 2:1-2:31
- Fabio Maschi, Gustavo Alonso:
Strega: An HTTP Server for FPGAs. 3:1-3:27 - Yunhui Qiu, Yiqing Mao, Xuchen Gao, Sichao Chen, Jiangnan Li, Wenbo Yin, Lingli Wang:
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism. 4:1-4:26 - John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis:
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology. 5:1-5:25 - Miguel Reis, Mário P. Véstias, Horácio C. Neto:
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. 6:1-6:30 - Rafael Fão de Moura, Luigi Carro:
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators. 7:1-7:19 - Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan:
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow. 8:1-8:26 - Louis Noyez, Nadia El Mrabet, Olivier Potin, Pascal Véron:
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2. 9:1-9:31 - Parastoo Soleimani, David W. Capson, Kin Fun Li:
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching. 10:1-10:21 - Olivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, G. Abarajithan, Nojan Sheybani, Andres Meza, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner:
Tailor: Altering Skip Connections for Resource-Efficient Inference. 11:1-11:23 - Jennifer Hasler, Cong Hao:
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis. 12:1-12:25
- Diana Göhringer, Georgios Keramidas, Akash Kumar:
Introduction to the FPL 2021 Special Section. 13:1-13:2 - Stefan Nikolic, Paolo Ienne:
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. 14:1-14:39 - Zhengyan Liu, Qiang Liu, Shun Yan, Ray C. C. Cheung:
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning. 15:1-15:20 - Jeffrey Chen, Sang-Woo Jun, Sehwan Hong, Warrick He, Jinyeong Moon:
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge. 16:1-16:25
- Sajjad Rostami Sani, Andy Gean Ye:
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. 17:1-17:29 - Yonggen Li, Xin Li, Haibin Shen, Jicong Fan, Yanfeng Xu, Kejie Huang:
An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration. 18:1-18:27
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