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2020 – today
- 2021
[c15]Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic:
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs. FPGA 2021: 11-22- 2020
- [c14]Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic:
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? DATE 2020: 1007-1010 - [c13]Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic:
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. FPGA 2020: 197-203 - [c12]Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic:
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. FPGA 2020: 204-210 - [c11]Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic:
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. FPGA 2020: 317 - [c10]Dina G. Mahmoud
, Wei Hu, Mirjana Stojilovic:
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. FPL 2020: 185-192 - [c9]Frédéric Gessler, Philip Brisk, Mirjana Stojilovic:
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSI Design 2020: 78-83 - [i2]Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic:
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. IACR Cryptol. ePrint Arch. 2020: 1494 (2020) - [i1]Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic:
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. IACR Cryptol. ePrint Arch. 2020: 1495 (2020)
2010 – 2019
- 2019
- [c8]Dina Mahmoud, Mirjana Stojilovic:
Timing Violation Induced Faults in Multi-Tenant FPGAs. DATE 2019: 1745-1750 - [c7]Dario Korolija, Mirjana Stojilovic:
Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform. FPGA 2019: 186 - [c6]Seyedeh Sharareh Mirzargar, Mirjana Stojilovic:
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. FPL 2019: 202-210 - [c5]Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT 2019: 10-18 - [c4]Dario Korolija, Mirjana Stojilovic:
FPGA-Assisted Deterministic Routing for FPGAs. IPDPS Workshops 2019: 155-162 - 2018
- [c3]Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk:
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL 2018: 21-25 - 2017
- [c2]Mirjana Stojilovic:
Parallel FPGA routing: Survey and challenges. FPL 2017: 1-8 - 2013
- [j1]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - 2012
- [c1]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548
Coauthor Index
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