default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDATE 2016: Dresden, Germany
- Luca Fanucci, Jürgen Teich:
2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. IEEE 2016, ISBN 978-3-9815-3707-9 - Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman, Muhammad Shafique:
Towards performance and reliability-efficient computing in the dark silicon era. 1-6 - Ali Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi, Marina Zapater, Andrea Bartolini, Pablo García Del Valle, David Atienza, Luca Benini, Babak Falsafi:
Towards near-threshold server processors. 7-12 - Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
Can beyond-CMOS devices illuminate dark silicon? 13-18 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque:
OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric Vehicles. 19-24 - Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schäfer:
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications. 25-30 - Daniel Thiele, Rolf Ernst:
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet. 31-36 - Shanker Shreejith, Bezborah Anshuman, Suhaib A. Fahmy:
Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems. 37-42 - Jian Kuang, Evangeline F. Y. Young:
Optimization for Multiple Patterning Lithography with cutting process and beyond. 43-48 - Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama:
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation. 49-54 - Woohyun Chung, Seongbo Shim, Youngsoo Shin:
Redundant via insertion in directed self-assembly lithography. 55-60 - Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. 61-66 - Yingnan Cui, Wei Zhang, Bingsheng He:
A discrete thermal controller for chip-multiprocessors. 67-72 - Simon J. Hollis, Steve Kerrison:
Swallow: Building an energy-transparent many-core embedded real-time system. 73-78 - Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. 79-84 - Xiuhong Li, Yun Liang:
Efficient kernel management on GPUs. 85-90 - Damien Hardy, Isabelle Puaut, Yiannakis Sazeides:
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. 91-96 - Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng:
A four-mode model for efficient fault-tolerant mixed-criticality systems. 97-102 - Eberle A. Rambo, Selma Saidi, Rolf Ernst:
Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip. 103-108 - Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Achieving 100% cell-aware coverage by design. 109-114 - Mahdi Nikdast, Gabriela Nicolescu, Jelena Trajkovic, Odile Liboiron-Ladouceur:
Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects. 115-120 - Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient spatial variation modeling via robust dictionary learning. 121-126 - Bohan Yang, Vladimir Rozic, Nele Mentens, Wim Dehaene, Ingrid Verbauwhede:
TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware. 127-132 - Maxime Lecomte, Jacques J. A. Fournier, Philippe Maurine:
On-chip fingerprinting of IC topology for integrity verification. 133-138 - Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Activation of logic encrypted chips: Pre-test or post-test? 139-144 - Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. 145-150 - Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy:
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks. 151-156 - Minho Ju, Hyeonggyu Kim, Soontae Kim:
Network delay-aware energy management for mobile systems. 157-162 - Sunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh, Anantha P. Chandrakasan:
Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs. 163-168 - Jens Trommer, Andre Heinzig, Tim Baldauf, Thomas Mikolajick, Walter M. Weber, Michael Raitza, Marcus Völp
:
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits. 169-174 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli:
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. 175-180 - Junchul Choi, Donghyun Kang, Soonhoi Ha:
Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems. 181-186 - Daniel Thiele, Rolf Ernst:
Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper. 187-192 - Alessandro Biondi, Giorgio C. Buttazzo:
Real-time analysis of engine control applications with speed estimation. 193-198 - Lin Li, Albrecht Mayer:
Trace-based analysis methodology of program flash contention in embedded multicore systems. 199-204 - Anteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing. 205-210 - Hsuan-Ming Huang, Yuwen Lin, Charles H.-P. Wen:
Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault. 211-216 - Marc Riera, Ramon Canal, Jaume Abella, Antonio González:
A detailed methodology to compute Soft Error Rates in advanced technologies. 217-222 - Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel:
Analysis of NBTI effects on high frequency digital circuits. 223-228 - Kai Huang, Biao Hu, Jan Botsch, Nikhil Madduri, Alois C. Knoll:
A scalable lane detection algorithm on COTSs with OpenCL. 229-232 - Dennis Hospach, Stefan Müller, Wolfgang Rosenstiel, Oliver Bringmann:
Simulation of falling rain for robustness testing of video-based surround sensing systems. 233-236 - Yusuke Sakumoto, Ittetsu Taniguchi:
Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid. 237-240 - Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama:
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern. 241-244 - Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin:
Practical ILP-based routing of standard cells. 245-248 - Daohang Shi, Azadeh Davoodi, Jeffrey T. Linderoth:
A procedure for improving the distribution of congestion in global routing. 249-252 - Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. 253-256 - Syed Md Jakaria Abdullah, Kai Lampka, Wang Yi:
Improving performance by monitoring while maintaining worst-case guarantees. 257-260 - Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Fault Tolerant Non-Volatile spintronic flip-flop. 261-264 - Yasser Moursy, Hao Zou, Ramy Iskander, Pierre Tisserand, Dieu-My Ton, Giuseppe Pasetti, Ehrenfried Seebacher, Alexander Steinmair, Thomas Gneiting, Heidrun Alius:
Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs. 265-268 - Zongbin Liu, Qinglong Zhang, Cunqing Ma, Changting Li, Jiwu Jing:
HPAZ: A high-throughput pipeline architecture of ZUC in hardware. 269-272 - Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto:
Towards a highly reliable SRAM-based PUFs. 273-276 - Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia:
Current based PUF exploiting random variations in SRAM cells. 277-280 - Taesik Na, Saibal Mukhopadhyay:
Behavioral modeling of timing slack variation in digital circuits due to power supply noise. 281-284 - Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen:
Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. 285-288 - Edoardo Fusella, Alessandro Cilardo:
PhoNoCMap: An application mapping tool for photonic networks-on-chip. 289-292 - Risat Mahmud Pathan:
Design of an efficient ready queue for earliest-deadline-first (EDF) scheduler. 293-296 - Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel:
RT level timing modeling for aging prediction. 297-300 - Bratislav Tasic, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G. J. Beelen, Roland Pulch:
Fast time-domain simulation for reliable fault detection. 301-306 - Wim Schoenmaker, Peter Meuris, Christian Strohm, Caren Tischendorf:
Holistic coupled field and circuit simulation. 307-312 - Nicodemus Banagaaya, Lihong Feng, Wim Schoenmaker, Peter Meuris, Aarnout Wieers, Renaud Gillon, Peter Benner:
Model Order Reduction for nanoelectronics coupled problems with many inputs. 313-318 - Piotr Putek, Peter Meuris, Roland Pulch, E. Jan W. ter Maten, Michael Gunther, Wim Schoenmaker, Frederik Deleu, Aarnout Wieers:
Shape optimization of a power MOS device under uncertainties. 319-324 - Oscar M. Guillen, Dawin Schmidt, Georg Sigl:
Practical evaluation of code injection in encrypted firmware updates. 325-330 - Yongje Lee, Jinyong Lee, Ingoo Heo, Dongil Hwang, Yunheung Paek:
Integration of ROP/JOP monitoring IPs in an ARM-based SoC. 331-336 - Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason M. Fung:
Verifying information flow properties of firmware using symbolic execution. 337-342 - Daniele Jahier Pagliari, Massimo Poncino, Enrico Macii:
Low-overhead adaptive constrast enhancement and power reduction for OLEDs. 343-348 - Andres Gomez, Lukas Sigrist, Michele Magno, Luca Benini, Lothar Thiele:
Dynamic energy burst scaling for transiently powered systems. 349-354 - Dinko Oletic, Vedran Bilas, Michele Magno, Norbert Felber, Luca Benini:
Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up. 355-360 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. 361-366 - Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu:
Design of latches and flip-flops using emerging tunneling devices. 367-372 - Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing. 373-378 - Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Distributed fair scheduling for many-cores. 379-384 - Kai Lampka, Björn Forsberg:
Keep it slow and in time: Online DVFS with hard real-time workloads. 385-390 - Yejia Di, Liang Shi, Kaijie Wu, Chun Jason Xue:
Exploiting process variation for retention induced refresh minimization on flash memory. 391-396 - Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Accurate synthesis of integrated RF passive components using surrogate models. 397-402 - Anindya Mukherjee, Andreas Pawlak, Michael Schröter, Didier Céli, Zoltan Huszka:
Implementation and quality testing for compact models implemented in Verilog-A. 403-408 - Ya Wang, Di Gao, Dani A. Tannir, Peng Li:
Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM. 409-414 - Stephan Herrmann, Wolfgang Utschick:
Availability and interpretability of optimal control for criticality estimation in vehicle active safety. 415-420 - Alon Ascoli, Ronald Tetzlaff, Leon O. Chua, John Paul Strachan, R. Stanley Williams:
Fading memory effects in a memristor for Cellular Nanoscale Network applications. 421-425 - Massimiliano Di Ventra, Fabio L. Traversa:
Digital Memcomputing Machines. 426 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli:
The Programmable Logic-in-Memory (PLiM) computer. 427-432 - Duo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb:
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits. 433-438 - David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine:
A fully-digital EM pulse detector. 439-444 - Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
On the development of a new countermeasure based on a laser attack RTL fault model. 445-450 - Qixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta:
Multi-story power distribution networks for GPUs. 451-456 - Alireza Shafaei, Massoud Pedram:
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques. 457-462 - Taeyoung Kim, Xin Huang, Hai-Bao Chen, Valeriy Sukharev, Sheldon X.-D. Tan:
Learning-based dynamic reliability management for dark silicon processor considering EM effects. 463-468 - Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. 469-474 - Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Conditional Deep Learning for energy-efficient and enhanced pattern recognition. 475-480 - Sai Zhang, Naresh R. Shanbhag:
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. 481-486 - Nicolas Ventroux, Tanguy Sassolas:
A new parallel SystemC kernel leveraging manycore architectures. 487-492 - Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann:
SystemC-link: Parallel SystemC simulation using time-decoupled segments. 493-498 - Leandro Gil, Martin Radetzki:
Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. 499-504 - Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld:
Built-in test of millimeter-Wave circuits based on non-intrusive sensors. 505-510 - Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi:
Adaptive delay monitoring for wide voltage-range operation. 511-516 - Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. 517-522 - Alexander Stühring, Günter Ehmen, Sibylle B. Fröschle:
Analyzing the impact of injected sensor data on an Advanced Driver Assistance System using the OP2TIMUS prototyping platform. 523-526 - Nicole Fern, Ismail San, Çetin Kaya Koç, Kwang-Ting Cheng:
Hardware Trojans in incompletely specified on-chip bus systems. 527-530 - Emanuele Del Sozzo, Gianluca C. Durelli, E. M. G. Trainiti, Antonio Miele, Marco D. Santambrogio, Cristiana Bolchini:
Workload-aware power optimization strategy for asymmetric multiprocessors. 531-534 - Anup Das, Geoff V. Merrett, Bashir M. Al-Hashimi:
The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation. 535-538 - Matina Maria Trompouki, Leonidas Kosmidis:
Towards general purpose computations on low-end mobile GPUs. 539-542 - S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi:
Estimating delay differences of arbiter PUFs using silicon data. 543-546 - Marc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud, Edith Kussener:
On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults. 547-550 - Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park:
Sequential analysis driven reset optimization to improve power, area and routability. 551-554 - Bo Liu, Anna Nikolaeva:
Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithm. 555-558 - Yuliia Romenska, Florence Maraninchi:
Efficient monitoring of loose-ordering properties for SystemC/TLM. 559-562 - K. Naveen, Dinesh Kumar Sharma:
Testable design of repeaterless low swing on-chip interconnect. 563-566 - Ta-Tung Yen, Bin Yu, Visvesh S. Sathe:
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. 567-570 - Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Domenico Rossi, Joseph Sawicki:
Panel: Looking backwards and forwards. 571-575 - Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel:
Aging-aware voltage scaling. 576-581 - Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
RECORD: Reducing register traffic for checkpointing in embedded processors. 582-587 - Philipp Schläfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek:
Error resilience and energy efficiency: An LDPC decoder design study. 588-593 - Apostolos Kokolis, Alexandros Mavrogiannis, Dimitrios Rodopoulos, Christos Strydis, Dimitrios Soudris:
Runtime interval optimization and dependable performance for application-level checkpointing. 594-599 - Benjamin A. Bjørnseth, Asbjørn Djupdal, Lasse Natvig:
A systematic approach to automated construction of power emulation models. 600-605 - Alessandro Danese, Graziano Pravadelli, Ivan Zandona:
Automatic generation of power state machines through dynamic mining of temporal assertions. 606-611 - Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
Approximation through logic isolation for the design of quality configurable circuits. 612-617 - Morten Chabert Eskesen, Paul Pop, Seetal Potluri:
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips. 618-623 - Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. 624-629 - Mohamed Ibrahim, Krishnendu Chakrabarty, Kristin Scott:
Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips. 630-635 - Amir Aminifar, Paulo Tabuada, Petru Eles, Zebo Peng:
Self-triggered controllers and hard real-time guarantees. 636-641 - Yuankun Xue, Saul Rodriguez, Paul Bogdan:
A spatio-temporal fractal model for a CPS approach to brain-machine-body interfaces. 642-647 - Nathan Allen, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Nitish D. Patel:
Modular code generation for emulating the electrical conduction system of the human heart. 648-653 - Juan Valencia, E. P. van Horssen, Dip Goswami, W. P. M. H. Heemels, Kees Goossens:
Resource utilization and Quality-of-Control trade-off for a composable platform. 654-659 - Haider A. F. Almurib, T. Nandha Kumar, Fabrizio Lombardi:
Inexact designs for approximate low power addition by cell replacement. 660-665 - Soumya Banerjee, Wenjing Rao:
A general approach for highly defect tolerant Parallel Prefix Adder design. 666-671 - Martin Omaña, A. Fiore, Cecilia Metra:
Inverters' self-checking monitors for reliable photovoltaic systems. 672-677 - Manolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Matús, Antimo Bruno, Per Stenström, Jérôme Martin, Yves Durand, Isabelle Dor:
EUROSERVER: Share-anything scale-out micro-server design. 678-683 - Oscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic:
Energy minimization at all layers of the data center: The ParaDIME project. 684-689 - Kostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos, Iordanis Koutsopoulos, K. Hasharoni, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends:
Rack-scale disaggregated cloud data centers: The dReDBox project vision. 690-695 - Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino:
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. 696-701 - José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni:
Enabling HPC for QoS-sensitive applications: The MANGO approach. 702-707 - Cristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea Rosario Beccari, Luca Benini, João Bispo, Radim Cmar, João M. P. Cardoso, Carlo Cavazzoni, Jan Martinovic, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna, Katerina Slaninová:
Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach. 708-713 - Valerio F. Annese, Marco Crepaldi, Danilo Demarchi, Daniela De Venuto:
A digital processor architecture for combined EEG/EMG falling risk prediction. 714-719 - Hantao Huang, Yuehua Cai, Hao Yu:
Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics. 720-725 - Dionisije Sopic, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation. 726-731 - Daniele Bortolotti, Bojan Milosevic, Andrea Bartolini, Elisabetta Farella, Luca Benini:
Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitor. 732-737 - Nicolas Estibals, Gaël Deest, Ali Hassan El Moussawi, Steven Derrien:
System level synthesis for virtual memory enabled hardware threads. 738-743 - Janarbek Matai, Dajung Lee, Alric Althoff, Ryan Kastner:
Composable, parameterizable templates for high-level synthesis. 744-749 - Benjamin Barrois, Karthick Parashar, Olivier Sentieys:
Leveraging power spectral density for scalable system-level accuracy evaluation. 750-755 - Hang Zhang, Nong Xiao, Fang Liu, Zhiguang Chen:
Leader: Accelerating ReRAM-based main memory by leveraging access latency discrepancy in crossbar arrays. 756-761 - Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen:
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache. 762-767 - Zheng Li, Fang Wang, Yu Hua, Wei Tong, Jingning Liu, Yu Chen, Dan Feng:
Exploiting more parallelism from write operations on PCM. 768-773 - Brendan A. Marcellino, Michael S. Hsiao:
Dynamic partitioning strategy to enhance symbolic execution. 774-779 - Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler:
Quantitative timing analysis of UML activity diagrams using statistical model checking. 780-785 - Arvind Ramanathan, Laura L. Pullum, Faraz Hussain, Dwaipayan Chakrabarty, Sumit Kumar Jha:
Integrating symbolic and statistical methods for testing intelligent systems: Applications to machine learning and computer vision. 786-791 - Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zain Navabi:
Path selection and sensor insertion flow for age monitoring in FPGAs. 792-797 - Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli:
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults. 798-803 - Cristiana Bolchini, Luca Cassano, Antonio Miele:
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. 804-809 - Shyamsundar Venkataraman, Rui Santos, Akash Kumar:
A flexible inexact TMR technique for SRAM-based FPGAs. 810-813 - Mohammad Fawaz, Farid N. Najm:
Accurate verification of RC power grids. 814-817 - Viacheslav Izosimov, Alexandros Asvestopoulos, Oscar Blomkvist, Martin Törngren:
Security-aware development of cyber-physical systems illustrated with automotive case study. 818-821 - Joost van Pinxten, Marc Geilen, Twan Basten, Umar Waqas, Lou J. Somers:
Online heuristic for the Multi-Objective Generalized traveling salesman problem. 822-825 - Zhiqi Zhu, Joseph Callenes-Sloan:
Towards low overhead control flow checking using regular structured control. 826-829 - Ioannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael, Theocharis Theocharides:
Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithms. 830-833 - Rainer Leupers:
Technology Transfer in computing systems: The TETRACOM approach. 834-837 - Loris Duch, Pablo García Del Valle, Shrikanth Ganapathy, Andreas Burg, David Atienza:
Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices. 838-841 - Niloofar Hezarjaribi, Ramin Fallahzadeh, Hassan Ghasemzadeh:
A machine learning approach for medication adherence monitoring using body-worn sensors. 842-845 - Weiwei Ai, Nitish D. Patel, Partha S. Roop:
Requirements-centric closed-loop validation of implantable cardiac devices. 846-849 - Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. 850-853 - Mohammad Hashem Haghbayan, Antonio Miele, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen:
A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era. 854-857 - Jason H. Gao, Li-Shiuan Peh:
Automotive V2X on phones: Enabling next-generation mobile ITS apps. 858-863 - Grigori Fursin, Anton Lokhmotov, Ed Plowman:
Collective Knowledge: Towards R&D sustainability. 864-869 - Martin Schoeberl:
Lessons learned from the EU project T-CREST. 870-875 - Jari Nurmi, Elena Simona Lohan:
MULTI-POS: Marie Curie network in multi-technology positioning. 876-881 - Jan Kuper, Lutz Schubert, Kilian Kempf, Colin W. Glass, Daniel Rubio Bonilla, Manuel Carro:
Program transformations in the POLCA project. 882-887 - Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Stasinos Konstantopoulos, Theodoros Giannakopoulos, Vangelis Karkaletsis, Vaggelis Mariatos:
Computation and communication challenges to deploy robots in assisted living environments. 888-893 - Ewald Wachmann, Sergio Saponara, Cristian Zambelli, Pierre Tisserand, J. Charbonnier, Tobias Erlbacher, S. Gruenler, C. Hartler, Jörg Siegert, Pierre Chassard, D. M. Ton, Lorenzo Ferrari, Luca Fanucci:
ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technology. 894-899 - Sen Ma, Zeyad Aklah, David Andrews:
Run time interpretation for creating custom accelerators. 900-905 - E. M. G. Trainiti, Gianluca C. Durelli, Antonio Miele, Cristiana Bolchini, Marco D. Santambrogio:
A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems. 906-911 - Achim Lösch, Tobias Beisel, Tobias Kenter, Christian Plessl, Marco Platzner:
Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. 912-917 - Pingfan Meng, Alric Althoff, Quentin Gautier, Ryan Kastner:
Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs. 918-923 - Konstantin Selyunin, Thang Nguyen, Ezio Bartocci, Dejan Nickovic, Radu Grosu:
Monitoring of MTL specifications with IBM's spiking-neuron model. 924-929 - Shafaq Iqtedar, Osman Hasan, Muhammad Shafique, Jörg Henkel:
Formal probabilistic analysis of distributed resource management schemes in on-chip systems. 930-935 - Reza Salkhordeh, Hossein Asadi:
An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. 936-941 - Zhiyong Zhang, Lei Ju, Zhiping Jia:
Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead. 942-947 - Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. 948-953 - Jelena Spasic, Di Liu, Todor P. Stefanov:
Exploiting resource-constrained parallelism in hard real-time streaming applications. 954-959 - XuanKhanh Do, Stéphane Louise, Albert Cohen:
Transaction Parameterized Dataflow: A model for context-dependent streaming applications. 960-965 - Christopher B. Harris, Ian G. Harris:
GLAsT: Learning formal grammars to translate natural language specifications into hardware assertions. 966-971 - Karsten Scheibler, Dominik Erb, Bernd Becker:
Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs. 972-977 - Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty:
Pre-bond testing of the silicon interposer in 2.5D ICs. 978-983 - Josef Kinseher, Leonardo Bonet Zordan, Ilia Polian, Andreas Leininger:
Improving SRAM test quality by leveraging self-timed circuits. 984-989 - Frank Piessens, Ingrid Verbauwhede:
Software security: Vulnerabilities and countermeasures for two attacker models. 990-999 - Gaoming Du, Yanghao Ou, Xiangyang Li, Ping Song, Zhonghai Lu, Minglun Gao:
OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction. 1000-1005 - Thiago Raupp da Rosa, Thomas Mesquida, Romain Lemaire, Fabien Clermidy:
MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures. 1006-1011 - Adam Kostrzewa, Selma Saidi, Rolf Ernst:
Slack-based resource arbitration for real-time Networks-on-Chip. 1012-1017 - Mahroo Zandrahimi, Zaid Al-Ars, Philippe Debaud, Armand Castillejo:
Challenges of using on-chip performance monitors for process and environmental variation compensation. 1018-1019 - Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel:
Study of workload impact on BTI HCI induced aging of digital circuits. 1020-1021 - Charly Bechara, Karim Ben Chehida, Mickaël Guibert, Renaud Schmit, Maria Lepecq, Laurent Soulier, Thomas Dombek, Yann Leclerc:
Fast prototyping platform for navigation systems with sensors fusion. 1022-1023 - Matthew M. Y. Kuo, Sidharta Andalam, Partha S. Roop:
Precision timed industrial automation systems. 1024-1025 - Ahmed M. Hamed, Mona Safar, M. Watheq El-Kharashi, Ashraf Salem:
AUTOSAR-based communication coprocessor for automotive ECUs. 1026-1027 - Daniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid:
Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing. 1028-1029 - Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Optimizing Majority-Inverter Graphs with functional hashing. 1030-1035 - An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou:
Resource-aware functional ECO patch generation. 1036-1041 - Gang Wu, Chris C. N. Chu:
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits. 1042-1047 - Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. 1048-1053 - John Adler, Djordje Maksimovic, Andreas G. Veneris:
Root-cause analysis for memory-locked errors. 1054-1059 - Ghaith Tarawneh, Andrey Mokhov, Alex Yakovlev:
Formal verification of clock domain crossing using gate-level models of metastable flip-flops. 1060-1065 - Maria A. Serrano, Alessandra Melani, Marko Bertogna, Eduardo Quiñones:
Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions. 1066-1071 - Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele:
Speed optimization for tasks with two resources. 1072-1077 - Wen-Hung Huang, Jian-Jia Chen:
Self-suspension real-time tasks under fixed-relative-deadline fixed-priority scheduling. 1078-1083 - Wei-Hen Lo, Kai-zen Liang, TingTing Hwang:
Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). 1084-1089 - Long Cheng, Kai Huang, Gang Chen, Biao Hu, Alois C. Knoll:
Minimizing peak temperature for pipelined hard real-time systems. 1090-1095 - Aryabartta Sahu:
Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor. 1096-1101 - Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. 1102-1111 - Kevin Zeng, Peter M. Athanas:
A q-gram birthmarking approach to predicting reusable hardware. 1112-1115 - Majid Jalili, Hamid Sarbazi-Azad:
Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memories. 1116-1119 - Mischa Moestl, Rolf Ernst:
Handling complex dependencies in system design. 1120-1123 - Anton Karputkin, Jaan Raik:
A synthesis-agnostic behavioral fault model for high gate-level fault coverage. 1124-1127 - Dan Trock, Rick Fisette:
Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargeting. 1128-1131 - Jo Laufenberg, Sebastian Reiter, Alexander Viehl, Oliver Bringmann, Thomas Kropf, Wolfgang Rosenstiel:
Combining graph-based guidance with error effect simulation for efficient safety analysis. 1132-1135 - Travis Boraten, Avinash Karanth Kodi:
Packet security with path sensitization for NoCs. 1136-1139 - Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto García Ortiz:
Synthesis of approximate coders for on-chip interconnects using reversible logic. 1140-1143 - Ayan Datta, James D. Warnock, Ankur Shukla, Saurabh Gupta, Yiu H. Chan, Karthik Mohan, Charudhattan Nagarajan:
Design-synthesis co-optimisation using skewed and tapered gates. 1144-1147 - Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni:
A synthesis-parameter tuning system for autonomous design-space exploration. 1148-1151 - Rajdeep Mukherjee, Peter Schrammel, Daniel Kroening, Tom Melham:
Unbounded safety verification for hardware using software analyzers. 1152-1155 - Ahmed Irfan, Alessandro Cimatti, Alberto Griggio, Marco Roveri, Roberto Sebastiani:
Verilog2SMV: A tool for word-level verification. 1156-1159 - Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards formal verification of real-world SystemC TLM peripheral models - a case study. 1160-1163 - Ying Wang, Huawei Li, Xiaowei Li:
Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. 1164-1167 - Zheng Wang, Georgios Karakonstantis, Anupam Chattopadhyay:
A low overhead error confinement method based on application statistical characteristics. 1168-1171 - Ruan de Clercq, Ronald De Keulenaer, Bart Coppens, Bohan Yang, Pieter Maene, Koen De Bosschere, Bart Preneel, Bjorn De Sutter, Ingrid Verbauwhede:
SOFIA: Software and control flow integrity architecture. 1172-1177 - Aurélien Francillon:
Trust, but verify: Why and how to establish trust in embedded devices. 1178-1182 - Michalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
CrossOver: Clock domain crossing under virtual-channel flow control. 1183-1188 - Rawan Abdel-Khalek, Valeria Bertacco:
Correct runtime operation for NoCs through adaptive-region protection. 1189-1194 - Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Reza Yazdani Aminabadi, Masoud Daneshtalab:
Fault-tolerant 3-D network-on-chip design using dynamic link sharing. 1195-1200 - Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini:
Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. 1201-1206 - Daniel Palomino, Muhammad Shafique, Altamiro Amadeu Susin, Jörg Henkel:
Thermal optimization using adaptive approximate computing for video coding. 1207-1212 - Hannes Plank, Gerald Holweg, Thomas Herndl, Norbert Druml:
High performance Time-of-Flight and color sensor fusion with image-guided depth super resolution. 1213-1218 - Stefan Scholl, Philipp Schläfer, Norbert Wehn:
Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware. 1219-1224 - Wenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang, Luca Daniel:
Utilizing macromodels in floating random walk based capacitance extraction. 1225-1230 - A. Lucas Martins, Jorge Fernandez Villena, Luís Miguel Silveira:
Variability and statistical analysis flow for dynamic linear systems with large number of inputs. 1231-1236 - Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Variation-aware near threshold circuit synthesis. 1237-1242 - Jinho Lee, Jung Ho Ahn, Kiyoung Choi:
Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. 1243-1248 - Marco A. Z. Alves, Matthias Diener, Paulo C. Santos, Luigi Carro:
Large vector extensions inside the HMC. 1249-1254 - Ming Liu, Sang Woo Jun, Sungjin Lee, Jamey Hicks, Arvind:
minFlash: A minimalistic clustered flash array. 1255-1260 - Daniele Cesarini, Andrea Marongiu, Luca Benini:
An optimized task-based runtime system for resource-constrained parallel accelerators. 1261-1266 - Nicola Bombieri, Federico Busato, Franco Fummi:
A fine-grained performance model for GPU architectures. 1267-1272 - Ang Li, Shuaiwen Leon Song, Akash Kumar, Eddy Z. Zhang, Daniel G. Chavarría-Miranda, Henk Corporaal:
Critical points based register-concurrency autotuning for GPUs. 1273-1278 - Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta:
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration. 1279-1284 - Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge:
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations. 1285-1290 - Shengcheng Wang, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty:
Thermal-aware TSV repair for electromigration in 3D ICs. 1291-1296 - Thorben Casper, Herbert De Gersem, Renaud Gillon, Tomás Gotthans, Tomas Kratochvil, Peter Meuris, Sebastian Schöps:
Electrothermal simulation of bonding wire degradation under uncertain geometries. 1297-1302 - Michael Waidner, Michael Kasper:
Security in industrie 4.0 - challenges and solutions for the fourth industrial revolution. 1303-1308 - Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems. 1309-1314 - Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore, Sujay Deb:
Adaptive multi-voltage scaling in wireless NoC for high performance low power applications. 1315-1320 - Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Energy efficient transceiver in wireless Network on Chip architectures. 1321-1326 - Mohsen Imani, Abbas Rahimi, Tajana Simunic Rosing:
Resistive configurable associative memory for approximate computing. 1327-1332 - Ali Pahlevan, Pablo García Del Valle, David Atienza:
Exploiting CPU-load and data correlations in multi-objective VM placement for geo-distributed data centers. 1333-1338 - Seyed Morteza Nabavinejad, Maziar Goudarzi:
Energy efficiency in cloud-based MapReduce applications through better performance estimation. 1339-1344 - Juan C. Salinas Hilburg, Marina Zapater, José Luis Risco-Martín, José Manuel Moya, José Luis Ayala:
Unsupervised power modeling of co-allocated workloads for energy efficiency in data centers. 1345-1350 - Farimah Farahmandi, Prabhat Mishra:
Automated test generation for Debugging arithmetic circuits. 1351-1356 - Mohamed Hassan, Hiren D. Patel:
MCXplore: An automated framework for validating memory controller designs. 1357-1362 - Debjyoti Bhattacharjee, Soumi Chattopadhyay, Ansuman Banerjee:
EAST: Efficient Assertion Simulation techniques. 1363-1368 - Siamack BeigMohammadi, Bijan Alizadeh:
Combinational trace signal selection with improved state restoration for post-silicon debug. 1369-1374 - Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Practical way halting by speculatively accessing halt tags. 1375-1380 - Georgios Tziantzioulis, Ali Murat Gok, S. M. Faisal, Nikolaos Hardavellas, Seda Ogrenci Memik, Srinivasan Parthasarathy:
Lazy Pipelines: Enhancing quality in approximate computing. 1381-1386 - Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini:
High-efficiency logarithmic number unit design based on an improved cotransformation scheme. 1387-1392 - Atul Rahman, Jongeun Lee, Kiyoung Choi:
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. 1393-1398 - Peng Sun, Alin Achim, Ian Hasler, Paul R. Hill, José L. Núñez-Yáñez:
Energy efficient video fusion with heterogeneous CPU-FPGA devices. 1399-1404 - Antonis Nikitakis, Ioannis Papaefstathiou:
Highly efficient reconfigurable parallel graph cuts for embedded vision. 1405-1410 - Sherif M. Saif, Mohamed Dessouky, M. Watheq El-Kharashi, Hazem M. Abbas, Salwa M. Nassar:
Pareto front analog layout placement using Satisfiability Modulo Theories. 1411-1416 - Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou:
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. 1417-1422 - Ye Wang, Constantine Caramanis, Michael Orshansky:
PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation. 1423-1428 - Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Reliability and performance trade-offs for 3D NoC-enabled multicore chips. 1429-1432 - Yuan Yao, Zhonghai Lu:
Memory-access aware DVFS for network-on-chip in CMPs. 1433-1436 - Awais Sani, Philippe Coussy, Cyrille Chavet:
A dynamically reconfigurable ECC decoder architecture. 1437-1440 - Vahideh Akhlaghi, Abbas Rahimi, Rajesh K. Gupta:
Resistive Bloom filters: From approximate membership to approximate computing with bounded errors. 1441-1444 - Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen:
Real-time system-level implementation of a telepresence robot using an embedded GPU platform. 1445-1448 - Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin:
Exploring specialized near-memory processing for data intensive operations. 1449-1452 - Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor:
Matlab to C compilation targeting Application Specific Instruction Set Processors. 1453-1456 - Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based buffer insertion for post-silicon yield improvement under process variability. 1457-1460 - Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty, Sanghamitra Roy:
PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms. 1461-1464 - Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli:
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. 1465-1468 - Muhammad Usman Karim Khan, Muhammad Shafique, Apratim Gupta, Thomas Schumann, Jörg Henkel:
Power-efficient load-balancing on heterogeneous computing platforms. 1469-1472 - Ahmed Nassar, Fadi J. Kurdahi, Salam R. Zantout:
Topaz: Mining high-level safety properties from logic simulation traces. 1473-1476 - Farimah Farahmandi, Prabhat Mishra, Sandip Ray:
Exploiting transaction level models for observability-aware post-silicon test generation. 1477-1480 - Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
SEERAD: A high speed yet energy-efficient rounding-based approximate divider. 1481-1484 - Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla:
Improving performance guarantees in wormhole mesh NoC designs. 1485-1488 - Tung Thanh Hoang, Amirali Shambayati, Andrew A. Chien:
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems. 1489-1492 - Pierre-Henri Horrein, Philip-Dylan Gleonec, Erwan Libessart, André Lalevee, Matthieu Arzel:
Ouessant: Flexible integration of dedicated coprocessors in Systems on Chip. 1493-1496 - Antonis Nikitakis, Ioannis Papaefstathiou, Konstantinos Makantasis, Anastasios D. Doulamis:
A novel background subtraction scheme for in-camera acceleration in thermal imagery. 1497-1500 - Marcos Sánchez-Élez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha:
Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA. 1501-1504 - Aurelio Morales-Villanueva, Rohit Kumar, Ann Gordon-Ross:
Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs. 1505-1508 - Hao Li, Fanshu Jiao, Alex Doboli:
Analog circuit topological feature extraction with unsupervised learning of new sub-structures. 1509-1512 - David Neves, Ricardo Martins, Nuno Lourenço, Nuno Horta:
Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach. 1513-1516 - Aydin Aysu, Shravya Gaddam, Harsha Mandadi, Carol Pinto, Luke Wegryn, Patrick Schaumont:
A design method for remote integrity checking of complex PCBs. 1517-1522 - Ryan Kastner, Wei Hu, Alric Althoff:
Quantifying hardware security using joint information flow analysis. 1523-1528 - Francesco Regazzoni, Paolo Ienne:
Instruction Set Extensions for secure applications. 1529-1534 - Yaw S. Obeng, Colm Nolan, David Brown:
Hardware security through chain assurance. 1535-1537 - Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, François-Xavier Standaert, Yier Jin:
Leverage Emerging Technologies For DPA-Resilient Block Cipher Design. 1538-1543 - An Chen, Xiaobo Sharon Hu, Yier Jin, Michael T. Niemier, Xunzhao Yin:
Using emerging technologies for hardware security beyond PUFs. 1544-1549 - Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita:
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. 1550-1555 - Carlos Moreno, Sean Kauffman, Sebastian Fischmeister:
Efficient program tracing and monitoring through power consumption - with a little help from the compiler. 1556-1561 - Kan Zhong, Duo Liu, Liang Liang, Linbo Long, Yi Lin, Zili Shao:
FLIC: Fast, lightweight checkpointing for mobile virtualization using NVRAM. 1562-1567 - Haeseung Lee, Hsinchung Chen, Mohammad Abdullah Al Faruque:
PAIS: Parallelization aware instruction scheduling for improving soft-error reliability of GPU-based systems. 1568-1573 - Simon Schulz, Oliver Bringmann:
Accelerating source-level timing simulation. 1574-1579 - Xiaoming Chen, Lixue Xia, Yu Wang, Huazhong Yang:
Sparsity-oriented sparse solver design for circuit simulation. 1580-1585 - Enrico Fraccaroli, Michele Lora, Sara Vinco, Davide Quaglia, Franco Fummi:
Integration of mixed-signal components into virtual platforms for holistic simulation of smart systems. 1586-1591 - Katsumi Okuda, Haruhiko Takeyama:
Decision tree generation for decoding irregular instructions. 1592-1597 - Jeckson Dellagostin Souza, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A reconfigurable heterogeneous multicore with a homogeneous ISA. 1598-1603 - Maurice Peemen, Runbin Shi, Sohan Lal, Ben H. H. Juurlink, Bart Mesman, Henk Corporaal:
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision. 1604-1609 - Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner:
Improving scalability of CMPs with dense ACCs coverage. 1610-1615 - Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr:
Hardware accelerator for analytics of sparse data. 1616-1621 - Alessandro Cilardo, Domenico Argenziano:
Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption. 1622-1627 - Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Throughput oriented FPGA overlays using DSP blocks. 1628-1633 - Qi Guo, Anderson Luiz Sartor, Anthony Brandon, Antonio C. S. Beck, Xuehai Zhou, Stephan Wong:
Run-time phase prediction for a reconfigurable VLIW processor. 1634-1639 - Freek Verbeek, Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh:
ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects. 1640-1645 - Leonie Ahrendts, Zain Alabedin Haj Hammadeh, Rolf Ernst:
Guarantees for runnable entities with heterogeneous real-time requirements. 1646-1651 - Zhenkun Yang, Kecheng Hao, Kai Cong, Li Lei, Sandip Ray, Fei Xie:
Validating scheduling transformation for behavioral synthesis. 1652-1657
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-08 20:41 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
