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ORCIDHossein Asadi 0001
Ghazanfar Asadi
Person information
- affiliation: Sharif University of Technology, Tehran, Iran
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2020 – today
- 2024
[j46]Mohammadamin Ajdari, Behrang Montazerzohour, Kimia Abdi, Hossein Asadi:
Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems. IEEE Comput. Archit. Lett. 23(2): 158-161 (2024)- [j45]Mostafa Kishani
, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi:
Joint Optimization of Communication and Storage Latencies for Vehicular Edge Computing. IEEE Trans. Intell. Transp. Syst. 25(6): 5435-5449 (2024) - [j44]Patrick Raaf, André Brinkmann, Eric Borba, Hossein Asadi, Sai Narasimhamurthy, John Bent, Mohamad El-Batal, Reza Salkhordeh:
From SSDs Back to HDDs: Optimizing VDO to Support Inline Deduplication and Compression for HDDs as Primary Storage Media. ACM Trans. Storage 20(4): 24:1-24:28 (2024) - [c46]Eric Borba, Reza Salkhordeh, Salim Mimouni, Eduardo Tavares, Paulo Maciel, Hossein Asadi, André Brinkmann:
A Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers. ARCS 2024: 266-281 - 2023
- [j43]Zeinab Seifoori, Behzad Omidi, Hossein Asadi:
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2075-2088 (2023) - [c45]Mohammadamin Ajdari, Pouria Peykani Sani, Amirhossein Moradi, Masoud Khanalizadeh Imani, Amir Hossein Bazkhanei, Hossein Asadi:
Re-architecting I/O Caches for Emerging Fast Storage Devices. ASPLOS (3) 2023: 542-555 - 2022
- [j42]Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann:
An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. Proc. ACM Meas. Anal. Comput. Syst. 6(2): 30:1-30:27 (2022) - [j41]Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. IEEE Trans. Computers 71(6): 1305-1319 (2022) - [j40]Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R. Rabiee, Hossein Asadi:
RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(3): 1492-1506 (2022) - [j39]Mojtaba Tarihi, Soheil Azadvar, Arash Tavakkol, Hossein Asadi, Hamid Sarbazi-Azad:
Quick Generation of SSD Performance Models Using Machine Learning. IEEE Trans. Emerg. Top. Comput. 10(4): 1821-1836 (2022) - [j38]Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi:
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. IEEE Trans. Parallel Distributed Syst. 33(10): 2304-2317 (2022) - [c44]Mostafa Kishani, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi:
Reducing Storage and Communication Latencies in Vehicular Edge Cloud. EuCNC 2022: 291-296 - [c43]Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann:
An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. SIGMETRICS (Abstracts) 2022: 59-60 - [i18]Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. CoRR abs/2201.02855 (2022) - [i17]Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi:
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. CoRR abs/2201.04373 (2022) - [i16]Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi:
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. CoRR abs/2202.13409 (2022) - 2021
- [j37]Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access 9: 115599-115619 (2021) - [j36]Saba Ahmadian, Farhad Taheri, Hossein Asadi:
Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. IEEE Trans. Emerg. Top. Comput. 9(4): 1914-1929 (2021) - [j35]Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi:
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. IEEE Trans. Parallel Distributed Syst. 32(10): 2415-2433 (2021) - [c42]Mostafa Kishani, Zdenek Becvar, Hossein Asadi:
PADSA: Priority-Aware Block Data Storage Architecture for Edge Cloud Serving Autonomous Vehicles. VNC 2021: 170-177 - [i15]Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi:
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. CoRR abs/2106.07423 (2021) - [i14]Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid Reza Rabiee, Hossein Asadi:
RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. CoRR abs/2111.03297 (2021) - [i13]Mostafa Kishani, Mehdi B. Tahoori, Hossein Asadi:
Dependability Analysis of Data Storage Systems in Presence of Soft Errors. CoRR abs/2112.12520 (2021) - [i12]Mostafa Kishani, Saba Ahmadian, Hossein Asadi:
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. CoRR abs/2112.12575 (2021) - 2020
- [j34]Mostafa Kishani, Saba Ahmadian, Hossein Asadi:
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. IEEE Trans. Computers 69(5): 649-665 (2020) - [j33]Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. IEEE Trans. Reliab. 69(2): 594-610 (2020) - [c41]Mostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi:
STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. DATE 2020: 1484-1489
2010 – 2019
- 2019
- [j32]Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi:
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J. Electron. Test. 35(2): 201-214 (2019) - [j31]Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi:
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. IEEE Trans. Computers 68(3): 455-470 (2019) - [j30]Reza Salkhordeh, Onur Mutlu, Hossein Asadi:
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. IEEE Trans. Computers 68(8): 1114-1130 (2019) - [j29]Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi:
An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 466-479 (2019) - [j28]Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi:
An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. IEEE Trans. Parallel Distributed Syst. 30(6): 1238-1250 (2019) - [j27]Mostafa Kishani, Mehdi Baradaran Tahoori, Hossein Asadi:
Dependability Analysis of Data Storage Systems in Presence of Soft Errors. IEEE Trans. Reliab. 68(1): 201-215 (2019) - [j26]Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi:
Estimating and Mitigating Aging Effects in Routing Network of FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 651-664 (2019) - [c40]Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. ASP-DAC 2019: 173-178 - [c39]Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. DATE 2019: 854-859 - [c38]Saba Ahmadian, Reza Salkhordeh, Hossein Asadi:
LBICA: A Load Balancer for I/O Cache Architectures. DATE 2019: 1196-1201 - [c37]Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT 2019: 10-18 - [i11]Reza Salkhordeh, Onur Mutlu, Hossein Asadi:
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. CoRR abs/1903.10067 (2019) - [i10]Saba Ahmadian, Farhad Taheri, Hossein Asadi:
Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. CoRR abs/1912.01555 (2019) - 2018
- [j25]Zeinab Seifoori, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi:
Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era. Adv. Comput. 110: 259-294 (2018) - [j24]Saba Ahmadian, Onur Mutlu, Hossein Asadi:
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. Proc. ACM Meas. Anal. Comput. Syst. 2(1): 9:1-9:34 (2018) - [j23]Behnam Khaleghi, Hossein Asadi:
A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2196-2209 (2018) - [j22]Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi:
ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. IEEE Trans. Parallel Distributed Syst. 29(7): 1605-1620 (2018) - [j21]Mostafa Kishani, Hossein Asadi:
Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. IEEE Trans. Reliab. 67(3): 1111-1127 (2018) - [c36]Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi:
Investigating power outage effects on reliability of solid-state drives. DATE 2018: 207-212 - [c35]Saba Ahmadian, Onur Mutlu, Hossein Asadi:
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. SIGMETRICS (Abstracts) 2018: 73 - [i9]Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi:
Investigating Power Outage Effects on Reliability of Solid-State Drives. CoRR abs/1805.00140 (2018) - [i8]Saba Ahmadian, Onur Mutlu, Hossein Asadi:
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. CoRR abs/1805.00976 (2018) - [i7]Reza Salkhordeh, Hossein Asadi:
An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture. CoRR abs/1805.02514 (2018) - [i6]Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi:
ReCA: an Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. CoRR abs/1805.06747 (2018) - [i5]Mostafa Kishani, Hossein Asadi:
Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. CoRR abs/1806.01352 (2018) - [i4]Mostafa Kishani, Reza Eftekhari, Hossein Asadi:
Evaluating Impact of Human Errors on the Availability of Data Storage Systems. CoRR abs/1806.01360 (2018) - [i3]Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi:
An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. CoRR abs/1812.04122 (2018) - [i2]Saba Ahmadian, Reza Salkhordeh, Hossein Asadi:
LBICA: A Load Balancer for I/O Cache Architectures. CoRR abs/1812.08720 (2018) - 2017
- [j20]Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi:
PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era. IEEE Trans. Computers 66(6): 982-995 (2017) - [c34]Mostafa Kishani, Reza Eftekhari, Hossein Asadi:
Evaluating impact of human errors on the availability of data storage systems. DATE 2017: 314-317 - [c33]Zeinab Seifoori, Behnam Khaleghi, Hossein Asadi:
A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. DATE 2017: 1342-1347 - 2016
- [j19]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46: 219-220 (2016) - [j18]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65(4): 1006-1009 (2016) - [j17]Mojtaba Tarihi, Hossein Asadi, Alireza Haghdoost, Mohammad Arjomand, Hamid Sarbazi-Azad:
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization. IEEE Trans. Computers 65(6): 1678-1691 (2016) - [j16]Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 367-379 (2016) - [j15]Hamed Farbeh, Nooshin Sadat Mirzadeh, Nahid Farhady Ghalaty, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi:
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3296-3309 (2016) - [j14]Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi:
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3489-3498 (2016) - [c32]Reza Salkhordeh, Hossein Asadi:
An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. DATE 2016: 936-941 - [c31]Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi:
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. FPL 2016: 1-8 - 2015
- [j13]Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi:
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE Embed. Syst. Lett. 7(2): 46-50 (2015) - [j12]Saeideh Alinezhad Chamazcoti, Ziba Delavari, Seyed Ghassem Miremadi, Hossein Asadi:
On endurance and performance of erasure codes in SSD-based storage systems. Microelectron. Reliab. 55(11): 2453-2467 (2015) - [j11]Reza Salkhordeh, Hossein Asadi, Shahriar Ebrahimi:
Operating system level data tiering using online workload characterization. J. Supercomput. 71(4): 1534-1562 (2015) - [j10]Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi:
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1868-1878 (2015) - [c30]Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi:
An efficient reconfigurable architecture by characterizing most frequent logic functions. FPL 2015: 1-6 - [c29]Mojtaba Tarihi, Hossein Asadi, Hamid Sarbazi-Azad:
DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling. SIGMETRICS 2015: 297-308 - 2014
- [j9]Hossein Asadi, Alireza Haghdoost, Morteza Ramezani, Nima Elyasi, Amirali Baniasadi:
CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors. Microelectron. Reliab. 54(5): 1009-1021 (2014) - [j8]Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli:
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectron. Reliab. 54(6-7): 1412-1420 (2014) - [j7]Sadegh Yazdanshenas, Hossein Asadi:
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 798-802 (2014) - [c28]Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori:
A power-efficient reconfigurable architecture using PCM configuration technology. DATE 2014: 1-6 - [c27]Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori:
Towards dark silicon era in FPGAs using complementary hard logic design. FPL 2014: 1-6 - [c26]Ali Ahari, Hossein Asadi, Mehdi Baradaran Tahoori:
Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. ReCoSoC 2014: 1-2 - 2013
- [j6]Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli:
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1454-1468 (2013) - [c25]Mohammad Hossein Hajkazemi, Amirali Baniasadi, Hossein Asadi:
FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. ASAP 2013: 153-159 - [c24]Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori:
CLASS: Combined logic and architectural soft error sensitivity analysis. ASP-DAC 2013: 601-607 - [c23]Mojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori:
A layout-based approach for multiple event transient analysis. DAC 2013: 100:1-100:6 - [c22]Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi:
FTSPM: A Fault-Tolerant ScratchPad Memory. DSN 2013: 1-10 - 2012
- [j5]Hossein Asadi, Mehdi Baradaran Tahoori, Mahdi Fazeli, Seyed Ghassem Miremadi:
Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron. Reliab. 52(6): 1215-1226 (2012) - 2011
- [c21]Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). DATE 2011: 70-75 - [c20]Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi:
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. DATE 2011: 298-292 - 2010
- [j4]Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error modeling and remediation techniques in ASIC designs. Microelectron. J. 41(8): 506-522 (2010) - [c19]Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori:
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. DSD 2010: 797-800 - [c18]Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian:
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. DSN 2010: 131-140 - [c17]Alireza Haghdoost, Hossein Asadi, Amirali Baniasadi:
System-Level Vulnerability Estimation for Data Caches. PRDC 2010: 157-164
2000 – 2009
- 2009
- [j3]Mehdi Baradaran Tahoori, Hossein Asadi, Brian Mullins, David R. Kaeli:
Obtaining FPGA soft error rate in high performance information systems. Microelectron. Reliab. 49(5): 551-557 (2009) - 2007
- [j2]Hossein Asadi, Mehdi Baradaran Tahoori:
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1320-1331 (2007) - [c16]Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti:
Estimating Error Propagation Probabilities with Bounded Variances. DFT 2007: 41-49 - [c15]Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano:
Case Study: Soft Error Rate Analysis in Storage Systems. VTS 2007: 256-264 - [i1]Ghazanfar Asadi, Mehdi Baradaran Tahoori:
An Accurate SER Estimation Method Based on Propagation Probability. CoRR abs/0710.4712 (2007) - 2006
- [j1]Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli:
Reducing Data Cache Susceptibility to Soft Errors. IEEE Trans. Dependable Secur. Comput. 3(4): 353-364 (2006) - [c14]Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli:
Vulnerability analysis of L2 cache elements to single event upsets. DATE 2006: 1276-1281 - [c13]Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error derating computation in sequential circuits. ICCAD 2006: 497-501 - [c12]Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error hardening for logic-level designs. ISCAS 2006 - 2005
- [c11]Ghazanfar Asadi, Mehdi Baradaran Tahoori:
An Accurate SER Estimation Method Based on Propagation Probability. DATE 2005: 306-307 - [c10]Hossein Asadi, Mehdi Baradaran Tahoori:
Soft Error Modeling and Protection for Sequential Elements. DFT 2005: 463-474 - [c9]Ghazanfar Asadi, Mehdi Baradaran Tahoori:
Soft error rate estimation and mitigation for SRAM-based FPGAs. FPGA 2005: 149-160 - [c8]Ghazanfar Asadi, Mehdi Baradaran Tahoori:
An analytical approach for soft error rate estimation in digital circuits. ISCAS (3) 2005: 2991-2994 - [c7]Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli:
Balancing Performance and Reliability in the Memory Hierarchy. ISPASS 2005: 269-279 - [c6]Ghazanfar Asadi, Mehdi Baradaran Tahoori:
Soft Error Mitigation for SRAM-Based FPGAs. VTS 2005: 207-212 - 2004
- [c5]Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali:
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. PRDC 2004: 327-332 - 2003
- [c4]Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi:
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN 2003: 479-488 - [c3]Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali:
Fault injection into SRAM-based FPGAs for the analysis of SEU effects. FPT 2003: 428-430 - 2002
- [c2]Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali:
Fast Prototyping with Co-operation of Simulation and Emulation. FPL 2002: 15-25 - [c1]Seyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi:
Speedup analysis in simulation-emulation co-operation. FPT 2002: 394-398