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ORCID34th FPL 2024: Torino, Italy
- 34th International Conference on Field-Programmable Logic and Applications, FPL 2024, Torino, Italy, September 2-6, 2024. IEEE 2024, ISBN 979-8-3315-3007-5
- Victor Van Wijhe, Vincent Sprave, Daniele Passaretti, Nikolaos Alachiotis, Gerrit Grutzeck, Thilo Pionteck, Steven van der Vlugt
:
Exploring the Versal AI Engines for Signal Processing in Radio Astronomy. 1-10 - Tobias Hahn, Stefan Wildermann, Jürgen Teich:
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. 11-18 - Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. 19-23 - Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
DynaRapid: Fast-Tracking from C to Routed Circuits. 24-32 - Soheil Gholami Shahrouz, Vaughn Betz:
The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs. 33-42 - Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan:
Better Together: Combining Analytical and Annealing Methods for FPGA Placement. 43-52 - Timothy Martin, Dani Maarouf, Gary Gréwal, Shawki Areibi:
A High-Performance Routing Engine for Large-Scale FPGAs. 53-59 - Philip Stachura, Guanyu Li, Xin Wu, Christian Plessl, Zhenman Fang:
SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs. 60-68 - Mario Doumet, Marius Stan, Mathew Hall, Vaughn Betz:
H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth Memory. 69-77 - Canberk Sönmez, Mohamed Shahawy, Cemalettin Cem Belentepe, Paolo Ienne:
FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs. 78-86 - Qianyu Cheng, Zhendong Zheng, Tianhao Jiang, Cheng Tang, Teng Wang, Lei Gong, Chao Wang, Xuehai Zhou:
SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs. 87-91 - Owen P. Lucas, Alan D. George:
Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs. 92-99 - Jan-Oliver Opdenhövel, Christoph Alt, Christian Plessl, Tobias Kenter:
StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs. 100-108 - Dylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien:
Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis. 109-117 - Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic:
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits. 118-125 - Zheyuan Zou, Cheng Tang, Lei Gong, Chao Wang, Xuehai Zhou:
FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design. 126-132 - Chao Fu, Zengshi Wang, Jun Han:
Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification. 133-139 - Marta Andronic, George A. Constantinides:
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. 140-148 - Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong:
PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. 149-155 - Xilai Dai, Yuzong Chen, Mohamed S. Abdelfattah:
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. 156-163 - Xiaobei Yan, Han Qiu, Tianwei Zhang:
UniGuard: A Unified Hardware-oriented Threat Detector for FPGA-based AI Accelerators. 164-170 - Jonas Bertels, Quinten Norga, Ingrid Verbauwhede:
A Better Kyber Butterfly for FPGAs. 171-177 - Hayden Cook, Jeffrey Goeders:
Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA. 178-186 - Taikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng, Vaughn Betz:
A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs. 187-196 - Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng:
Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines. 197-203 - Geng Yang, Jie Lei, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li:
SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions. 204-212 - Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang:
CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. 213-219 - M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
IMAGine: An In-Memory Accelerated GEMV Engine Overlay. 220-226 - Xiaodong Deng, Shijie Wang, Tianyi Gao, Jing Liu, Longjun Liu, Nanning Zheng:
AMA: An Analytical Approach to Maximizing the Efficiency of Deep Learning on Versal AI Engine. 227-235 - Samuel Wiggins, Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna:
A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning. 236-242 - Kejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Yang Liu, Jun Yu, Kun Wang:
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA. 243-249 - Shadi Matinizadeh, Anup Das:
An Open-Source And Extensible Framework for Fast Prototyping and Benchmarking of Spiking Neural Network Hardware. 250-256 - Zhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis, Yiren Zhao:
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator. 257-263 - Geng Yang, Yanyue Xie, Zhong Jia Xue, Sung-En Chang, Yanyu Li, Peiyan Dong, Jie Lei, Weiying Xie, Yanzhi Wang, Xue Lin, Zhenman Fang:
SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs. 264-273 - Mahboobe Sadeghipour Roodsari, Jonas Krautter, Vincent Meyers, Mehdi B. Tahoori:
E3HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices. 274-280 - Cornelia Wulf, Gökhan Akgün, Mehdi Safarpour, Anastacia Grishchenko, Diana Göhringer:
Energy-Aware Synchronization of Hardware Tasks in Virtualized Embedded Systems. 281-287 - Sergey Gribok, Martin Langhammer, Bogdan Pasca:
FPGA Modular Multipliers using Hybrid Reduction Techniques. 288-296 - Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra:
Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. 297-303 - Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides:
Exploring FPGA designs for MX and beyond. 304-310 - Afzal Ahmad, Linfeng Du, Wei Zhang:
Fast and Practical Strassen's Matrix Multiplication using FPGAs. 311-317 - Abdul Wadood, Alec Lu, Ken Zhang, Zhenman Fang:
FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines. 318-324 - Kenneth Liu, Alec Lu, Zhenman Fang:
BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling. 325-331 - Zhendong Zheng, Qianyu Cheng, Teng Wang, Lei Gong, Xianglan Chen, Cheng Tang, Chao Wang, Xuehai Zhou:
LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization. 332-338 - Xuanzheng Wang, Shuo Miao, Peng Qu, Youhui Zhang:
DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model. 339-345 - Shangrong Li, Kai Liu, Wei Liu, Zibo Guo:
CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural Radiation Field Rendering. 346-352
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