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ORCIDEarl E. Swartzlander Jr.
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- affiliation: University of Texas at Austin, USA
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2020 – today
- 2020
[c130]Stafford Hutchins, Earl E. Swartzlander Jr.:
A Bfloat16 Fused Multiplier-Adder. UEMCON 2020: 52-55
2010 – 2019
- 2019
- [j89]Weiqiang Liu
, Tian Cao, Peipei Yin, Yuying Zhu, Chenghua Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Design and Analysis of Approximate Redundant Binary Multipliers. IEEE Trans. Computers 68(6): 804-819 (2019) - [c129]Alexander J. Groszewski, Earl E. Swartzlander Jr.:
A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. ACSSC 2019: 608-613 - [c128]Trenton J. Grale, Earl E. Swartzlander Jr.:
Parallel GF(2n) Modular Squarers. MWSCAS 2019: 872-875 - [p5]K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr.:
Memristor-Based Addition and Multiplication. Handbook of Memristor Networks 2019: 1123-1136 - 2018
- [j88]Lizy K. John, Earl E. Swartzlander Jr.:
Memristor-Based Computing. IEEE Micro 38(5): 5-6 (2018) - [j87]Weiqiang Liu, Faqiang Mei, Chenghua Wang, Máire O'Neill, Earl E. Swartzlander Jr.:
Data Compression Device Based on Modified LZ4 Algorithm. IEEE Trans. Consumer Electron. 64(1): 110-117 (2018) - [j86]Xiao-Ping Cui, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. J. Signal Process. Syst. 90(3): 409-419 (2018) - [j85]Peipei Yin, Chenghua Wang, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications. J. Signal Process. Syst. 90(4): 641-654 (2018) - [c127]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Memristor Adder Design. MWSCAS 2018: 314-317 - 2017
- [j84]Xiao-Ping Cui, Wenwen Dong, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi:
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. IEEE Trans. Computers 66(12): 1994-2004 (2017) - [j83]Lauren Guckert, Earl E. Swartzlander Jr.:
MAD Gates - Memristor Logic Design Using Driver Circuitry. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 171-175 (2017) - [j82]Lauren Guckert, Earl E. Swartzlander Jr.:
Optimized Memristor-Based Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 373-385 (2017) - [j81]Weiqiang Liu, Earl E. Swartzlander Jr., Máire O'Neill:
Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. IEEE Trans. Emerg. Top. Comput. 5(2): 148-150 (2017) - [c126]Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr.:
The future of computing - Arithmetic circuits implemented with memristors. ACSSC 2017: 745-749 - [c125]Trenton J. Grale, Earl E. Swartzlander Jr.:
Parallel GF(2n) multipliers. ACSSC 2017: 1029-1033 - [c124]Lauren Guckert, Earl E. Swartzlander Jr.:
Dadda Multiplier designs using memristors. ICICDT 2017: 1-4 - 2016
- [j80]Xiao-Ping Cui, Weiqiang Liu, Chen Xin, Earl E. Swartzlander Jr., Fabrizio Lombardi:
A Modified Partial Product Generator for Redundant Binary Multipliers. IEEE Trans. Computers 65(4): 1165-1171 (2016) - [j79]Jongwook Sohn, Earl E. Swartzlander Jr.:
A Fused Floating-Point Four-Term Dot Product Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(3): 370-378 (2016) - [c123]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Memristor based adder circuit design. ACSSC 2016: 162-166 - [c122]Lauren Guckert, Earl E. Swartzlander Jr.:
Optimized memristor-based ripple carry adders. ACSSC 2016: 1575-1579 - [c121]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Arithmetic circuit design with memristor based high fan-out logic gates. UEMCON 2016: 1-6 - 2015
- [j78]Weiqiang Liu, Earl E. Swartzlander Jr.:
Design of 3-D quantum-dot cellular automata adders. IEICE Electron. Express 12(6): 20150195 (2015) - [c120]Robert J. Ascott, Earl E. Swartzlander Jr.:
Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). ACSSC 2015: 182-185 - [c119]Mike O'Connor, Earl E. Swartzlander Jr.:
Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. ACSSC 2015: 722-726 - [c118]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Low-Cost Duplicate Multiplication. ARITH 2015: 2-9 - 2014
- [j77]Inwook Kong, Seong-Wan Kim, Earl E. Swartzlander Jr.:
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata. IEEE Trans. Computers 63(10): 2620-2625 (2014) - [j76]Jongwook Sohn, Earl E. Swartzlander Jr.:
A Fused Floating-Point Three-Term Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2842-2850 (2014) - [c117]Kihwan Jun, Earl E. Swartzlander Jr.:
Improved non-restoring square root algorithm with dual path calculation. ACSSC 2014: 1243-1246 - [c116]Divya Mahajan, Matheen Musaddiq, Earl E. Swartzlander Jr.:
Memristor based adders. ACSSC 2014: 1256-1260 - [p4]Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic. Computing Handbook, 3rd ed. (1) 2014: 20: 1-28 - [p3]Weiqiang Liu, Saket Srivastava, Máire O'Neill, Earl E. Swartzlander Jr.:
Security Issues in QCA Circuit Design - Power Analysis Attacks. Field-Coupled Nanocomputing 2014: 194-222 - 2013
- [j75]Earl E. Swartzlander Jr.:
STARS: Electronic Calculators: Desktop to Pocket. Proc. IEEE 101(12): 2558-2562 (2013) - [j74]Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
QCA Systolic Array Design. IEEE Trans. Computers 62(3): 548-560 (2013) - [j73]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 228-241 (2013) - [c115]Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr.:
Implementation of a high speed multiplier using carry lookahead adders. ACSSC 2013: 400-404 - [c114]Michael B. Sullivan, Earl E. Swartzlander Jr.:
On separable error detection for addition. ACSSC 2013: 2181-2186 - [c113]Jongwook Sohn, Earl E. Swartzlander Jr.:
Improved Architectures for a Floating-Point Fused Dot Product Unit. IEEE Symposium on Computer Arithmetic 2013: 41-48 - [c112]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Truncated Logarithmic Approximation. IEEE Symposium on Computer Arithmetic 2013: 191-198 - [c111]Jae Hong Min, Earl E. Swartzlander Jr.:
Fused floating-point two-term sum-of-squares unit. ASAP 2013: 147-152 - [c110]Hani H. Saleh, Baker S. Mohammad, Earl E. Swartzlander Jr.:
The optimum Booth radix for low power integer multipliers. IDT 2013: 1-4 - [c109]Weiqiang Liu, Saket Srivastava, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Power analysis attack of QCA circuits: A case study of the Serpent cipher. ISCAS 2013: 2075-2078 - [c108]Kihwan Jun, Earl E. Swartzlander Jr.:
Improved non-restoring division algorithm with dual path calculation. MWSCAS 2013: 1379-1382 - [c107]Jae Hong Min, Earl E. Swartzlander Jr.:
Fused floating-point magnitude unit. MWSCAS 2013: 1383-1386 - 2012
- [j72]Hyesook Lim, Soohyun Lee, Earl E. Swartzlander Jr.:
A new hierarchical packet classification algorithm. Comput. Networks 56(13): 3010-3022 (2012) - [j71]Earl E. Swartzlander Jr., Hani H. Saleh:
FFT Implementation with Fused Floating-Point Operations. IEEE Trans. Computers 61(2): 284-288 (2012) - [j70]Jongwook Sohn, Earl E. Swartzlander Jr.:
Improved Architectures for a Fused Floating-Point Add-Subtract Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2285-2291 (2012) - [c106]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Truncated error correction for flexible approximate multiplication. ACSCC 2012: 355-359 - [c105]Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
A review of QCA adders and metrics. ACSCC 2012: 747-751 - [c104]Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr.:
A low-power dual-path floating-point fused add-subtract unit. ACSCC 2012: 998-1002 - [c103]Kihwan Jun, Earl E. Swartzlander Jr.:
Modified non-restoring division algorithm with improved delay profile and error correction. ACSCC 2012: 1460-1464 - [c102]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Long Residue Checking for Adders. ASAP 2012: 177-180 - [c101]Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Cost-efficient decimal adder design in Quantum-dot cellular automata. ISCAS 2012: 1347-1350 - [c100]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86 - [c99]Sreenivaas Muthyala Sudhakar, Kumar P. Chidambaram, Earl E. Swartzlander Jr.:
Hybrid Han-Carlson adder. MWSCAS 2012: 818-821 - 2011
- [j69]Inwook Kong, Earl E. Swartzlander Jr.:
A Goldschmidt Division Method With Faster Than Quadratic Convergence. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 696-700 (2011) - [j68]Waqas Akram, Earl E. Swartzlander Jr.:
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. J. Signal Process. Syst. 65(2): 199-210 (2011) - [c98]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Hybrid residue generators for increased efficiency. ACSCC 2011: 144-148 - [c97]Jae Hong Min, Seong-Wan Kim, Earl E. Swartzlander Jr.:
A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. ACSCC 2011: 520-524 - [c96]Andrew G. Shafer, Lyndsi R. Parker, Earl E. Swartzlander Jr.:
The fully-serial pipelined multiplier. ACSCC 2011: 1817-1822 - [c95]Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Design rules for Quantum-dot Cellular Automata. ISCAS 2011: 2361-2364 - [c94]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [e2]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 [contents] - 2010
- [j67]Terence K. Rodrigues, Earl E. Swartzlander Jr.:
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. IEEE Trans. Computers 59(4): 522-531 (2010) - [j66]Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.:
Priority Tries for IP Address Lookup. IEEE Trans. Computers 59(6): 784-794 (2010) - [j65]Ron S. Waters, Earl E. Swartzlander Jr.:
A Reduced Complexity Wallace Multiplier Reduction. IEEE Trans. Computers 59(8): 1134-1137 (2010) - [j64]Inwook Kong, Earl E. Swartzlander Jr.:
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. IEEE Trans. Computers 59(12): 1703-1708 (2010) - [c93]Waqas Akram, Earl E. Swartzlander Jr.:
A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. ICASSP 2010: 1534-1537 - [c92]Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
QCA Systolic Matrix Multiplier. ISVLSI 2010: 149-154 - [c91]Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham:
High speed recursion-free CORDIC architecture. SoCC 2010: 65-70
2000 – 2009
- 2009
- [j63]Heumpil Cho, Earl E. Swartzlander Jr.:
Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Trans. Computers 58(6): 721-727 (2009) - [c90]Bassam Jamil Mohd, Earl E. Swartzlander Jr.:
A Power-Scalable Switch-Based Multi-processor FFT. ASAP 2009: 114-120 - [c89]Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim:
Design of a Goldschmidt iterative divider for quantum-dot cellular automata. NANOARCH 2009: 47-50 - [c88]Robert J. Ascott, Earl E. Swartzlander Jr.:
JavaFlow - A Java dataflow machine. SoCC 2009: 211-214 - [c87]Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
ASIC evaluation of ECHO hash function. SoCC 2009: 387-390 - 2008
- [j62]Youngmoon Choi, Earl E. Swartzlander Jr.:
Speculative Carry Generation With Prefix Adder. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 321-326 (2008) - [j61]Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds:
Bridge Floating-Point Fused Multiply-Add Design. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1727-1731 (2008) - [j60]Robert T. Grisamore, Earl E. Swartzlander Jr.:
Negative Save Sign Extension for Multi-term Adders and Multipliers. J. Signal Process. Syst. 52(1): 1-11 (2008) - [j59]Earl E. Swartzlander Jr.:
Systolic FFT Processors: A Personal Perspective. J. Signal Process. Syst. 53(1-2): 3-14 (2008) - [c86]Vijay K. Jain, Earl E. Swartzlander Jr.:
32 bit single cycle nonlinear VLSI cell for the ICA algorithm. ICASSP 2008: 1429-1432 - [c85]Hani H. Saleh, Earl E. Swartzlander Jr.:
A floating-point fused dot-product unit. ICCD 2008: 427-431 - [c84]Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.:
High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374 - [p2]Eric Quinnell, Earl E. Swartzlander Jr.:
Floating-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008 - [p1]Earl E. Swartzlander Jr.:
Fixed-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j58]Earl E. Swartzlander Jr.:
The Negative Two's Complement Number System. J. VLSI Signal Process. 49(1): 177-183 (2007) - [c83]Heumpil Cho, Earl E. Swartzlander Jr.:
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. IEEE Symposium on Computer Arithmetic 2007: 7-15 - [c82]Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD 2007: 7-12 - [c81]Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz:
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. VLSI-SoC (Selected Papers) 2007: 1-22 - [c80]Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC 2007: 194-199 - 2006
- [j57]Chang Yong Kang, Earl E. Swartzlander Jr.:
Digit-pipelined direct digital frequency synthesis based on differential CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1035-1044 (2006) - [c79]Tung N. Pham, Earl E. Swartzlander Jr.:
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. ASAP 2006: 105-108 - [c78]Earl E. Swartzlander Jr.:
Systolic FFT Processors: Past, Present and Future. ASAP 2006: 153-158 - 2005
- [c77]Youngmoon Choi, Earl E. Swartzlander Jr.:
Parallel Prefix Adder Design with Matrix Representation. IEEE Symposium on Computer Arithmetic 2005: 90-98 - [c76]Moboluwaji O. Sanu, Earl E. Swartzlander Jr.:
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ASAP 2005: 134-139 - [c75]Earl E. Swartzlander Jr.:
Three Dimensional System on Chip Technology, invited. IWSOC 2005: 465-470 - 2004
- [c74]Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase:
Parallel Montgomery Multipliers. ASAP 2004: 63-72 - [c73]Earl E. Swartzlander Jr.:
A Review of Large Parallel Counter Designs. ISVLSI 2004: 89-98 - 2003
- [j56]Mohammad Ibrahim, Earl E. Swartzlander Jr.:
Guest Editorial. J. VLSI Signal Process. 33(1-2): 5 (2003) - [c72]Ayman M. El-Khashab, Earl E. Swartzlander Jr.:
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ASAP 2003: 378-388 - [c71]Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.:
Quadruple Time Redundancy Adders. DFT 2003: 250-256 - [c70]Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.:
A self-testing method for the pipelined A/D converter. ISCAS (1) 2003: 109-112 - 2002
- [j55]Sungwook Yu, Earl E. Swartzlander Jr.:
A scaled DCT architecture with the CORDIC algorithm. IEEE Trans. Signal Process. 50(1): 160-167 (2002) - [j54]Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. J. VLSI Signal Process. 31(2): 77-89 (2002) - [c69]Chang Yong Kang, Earl E. Swartzlander Jr.:
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ASAP 2002: 111-119 - [c68]Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. ASAP 2002: 335-343 - 2001
- [j53]Sungwook Yu, Earl E. Swartzlander Jr.:
DCT Implementation with Distributed Arithmetic. IEEE Trans. Computers 50(9): 985-991 (2001) - [j52]Sungwook Yu, Earl E. Swartzlander Jr.:
A pipelined architecture for the multidimensional DFT. IEEE Trans. Signal Process. 49(9): 2096-2102 (2001) - [c67]K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte:
Analysis of Column Compression Multipliers. IEEE Symposium on Computer Arithmetic 2001: 33-39 - [c66]Tat Ngai, Earl E. Swartzlander Jr., Chen He:
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. DFT 2001: 78-83 - [c65]Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A fast hybrid carry-lookahead/carry-select adder design. ACM Great Lakes Symposium on VLSI 2001: 149-152 - [c64]Jae-Hyuck Kwak, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-shared TMR for fault-tolerant CORDIC processors. ICASSP 2001: 1241-1244 - 2000
- [j51]Michael J. Schulte, Earl E. Swartzlander Jr.:
A Family of Variable-Precision Interval Arithmetic Processors. IEEE Trans. Computers 49(5): 387-397 (2000) - [j50]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. IEEE Trans. Computers 49(6): 588-595 (2000) - [j49]Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.:
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. IEEE Trans. Computers 49(12): 1297-1309 (2000) - [j48]Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr.:
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. J. VLSI Signal Process. 25(2): 167-177 (2000) - [c63]Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. ASAP 2000: 235- - [c62]Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri:
Fault-Tolerant High-Performance Cordic Processors. DFT 2000: 164-172
1990 – 1999
- 1999
- [j47]Francescomaria Marino, Earl E. Swartzlander Jr.:
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. IEEE Trans. Computers 48(9): 951-961 (1999) - [j46]Hyesook Lim, Earl E. Swartzlander Jr.:
Multidimensional systolic arrays for the implementation of discrete Fourier transforms. IEEE Trans. Signal Process. 47(5): 1359-1370 (1999) - [j45]Francescomaria Marino, Vincenzo Piuri, Earl E. Swartzlander Jr.:
A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications. IEEE Trans. Signal Process. 47(11): 3179-3184 (1999) - [c61]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Power Consumption in Fast Dividers Using Time Shared TMR. DFT 1999: 256-264 - [c60]Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. DFT 1999: 265-273 - [c59]Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.:
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. ICCD 1999: 68-72 - [c58]Gwangwoo Choe, Earl E. Swartzlander Jr.:
Bipolar merged arithmetic for wavelet architectures. ISCAS (3) 1999: 462-465 - 1998
- [j44]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 20(1): 67-76 (1998) - [j43]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 20(3): 72-73 (1998) - [j42]Earl E. Swartzlander Jr.:
VLSI, MCM, and WSI: A Design Comparison. IEEE Des. Test Comput. 15(3): 28-34 (1998) - [j41]Mary Jane Irwin, Sun-Yuan Kung, Earl E. Swartzlander Jr.:
Editorial Message. J. VLSI Signal Process. 18(1): 7-8 (1998) - [c57]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Error-Correcting Goldschmidt Dividers Using Time Shared TMR. DFT 1998: 224-232 - [c56]Gwangwoo Choe, Earl E. Swartzlander Jr.:
Merged Arithmetic for Computing Wavelet Transforms. Great Lakes Symposium on VLSI 1998: 196-201 - [c55]Moises E. Robinson, Earl E. Swartzlander Jr.:
A reduction scheme to optimize the Wallace multiplier. ICCD 1998: 122-127 - 1997
- [j40]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 19(1): 74-75 (1997) - [j39]Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Hybrid CORDIC Algorithms. IEEE Trans. Computers 46(11):