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ORCIDRobert K. Brayton
Person information
- affiliation: University of California, Berkeley, USA
- award (2006): Paris Kanellakis Award
- award (2006): IEEE Emanuel R. Piore Award
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2020 – today
- 2024
[i4]Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton:
Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR abs/2406.06241 (2024)- 2022
- [j61]Siang-Yun Lee
, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2573-2586 (2022) - 2021
- [c249]He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton:
Deep Integration of Circuit Simulator and SAT Solver. DAC 2021: 877-882 - 2020
- [i3]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
Simulation-Guided Boolean Resubstitution. CoRR abs/2007.02579 (2020)
2010 – 2019
- 2019
- [j60]Yu-Yun Dai, Robert K. Brayton:
Verification and Synthesis of Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 366-379 (2019) - 2018
- [c248]Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton:
SAT-based area recovery in structural technology mapping. ASP-DAC 2018: 586-591 - [c247]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c246]Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. DAC 2018: 52:1-52:6 - [c245]Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. DATE 2018: 309-314 - [c244]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. DATE 2018: 755-760 - [p2]Yu-Yun Dai, Robert K. Brayton:
Identifying Transparent Logic in Gate-Level Circuits. Advanced Logic Synthesis 2018: 103-124 - 2017
- [c243]Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis:
Fast-extract with cube hashing. ASP-DAC 2017: 145-150 - [c242]Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton:
Property directed reachability with word-level abstraction. FMCAD 2017: 132-139 - [c241]Yu-Yun Dai, Robert K. Brayton:
Circuit recognition with deep learning. HOST 2017: 162 - [c240]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - 2016
- [j59]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 919-930 (2016) - [c239]Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton:
Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD 2016: 65-72 - [c238]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c237]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [c236]Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton:
2QBF: Challenges and Solutions. SAT 2016: 453-469 - 2015
- [j58]Robert K. Brayton, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa:
Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]. Proc. IEEE 103(11): 1952-1957 (2015) - [j57]Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton:
Component-Based Design by Solving Language Equations. Proc. IEEE 103(11): 2152-2167 (2015) - [c235]Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton:
Sequential equivalence checking of clock-gated circuits. DAC 2015: 51:1-51:6 - [c234]Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Bi-Decomposition Using Boolean Relations. DSD 2015: 72-78 - [c233]Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton:
Simulation Graphs for Reverse Engineering. FMCAD 2015: 152-159 - [c232]Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene:
Technology Mapping into General Programmable Cells. FPGA 2015: 70-73 - [c231]Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko:
Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops 2015: 281-296 - 2014
- [j56]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 305-317 (2014) - [c230]Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC 2014: 250-255 - [c229]Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB 2014: 623-624 - 2013
- [c228]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma:
A semi-canonical form for sequential AIGs. DATE 2013: 797-802 - [c227]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla:
GLA: gate-level abstraction revisited. DATE 2013: 1399-1404 - [c226]Jiang Long, Robert K. Brayton, Michael L. Case:
LEC: Learning Driven Data-path Equivalence Checking. DIFTS@FMCAD 2013 - [c225]Sayak Ray, Robert K. Brayton:
Ranking structure in communication fabrics. MEMOCODE 2013: 65-74 - 2012
- [c224]Sayak Ray, Robert K. Brayton:
Scalable progress verification in credit-based flow-control systems. DATE 2012: 905-910 - [c223]Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. DATE 2012: 1579-1584 - 2011
- [j55]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 651-664 (2011) - [j54]Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4(4): 34:1-34:23 (2011) - [c222]Niklas Eén, Alan Mishchenko, Robert K. Brayton:
Efficient implementation of property directed reachability. FMCAD 2011: 125-134 - [c221]Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton:
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD 2011 - [c220]Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets:
Delay optimization using SOP balancing. ICCAD 2011: 375-382 - 2010
- [j53]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. 27(2): 68-74 (2010) - [j52]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. 27(3): 62-74 (2010) - [c219]Robert K. Brayton, Alan Mishchenko:
ABC: An Academic Industrial-Strength Verification Tool. CAV 2010: 24-40 - [c218]Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton:
Combinational techniques for sequential equivalence checking. FMCAD 2010: 145-149 - [c217]Alan Mishchenko, Robert K. Brayton, Stephen Jang:
Global delay optimization using structural choices. FPGA 2010: 181-184 - [p1]Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Yves Crama, Peter L. Hammer:
Synthesis of Multilevel Boolean Networks. Boolean Models and Methods 2010: 675-722
2000 – 2009
- 2009
- [c216]Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton:
Speculative reduction-based scalable redundancy identification. DATE 2009: 1674-1679 - [c215]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith:
Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703 - [c214]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160 - [c213]Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240 - 2008
- [j51]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Compositionally Progressive Solutions of Synchronous FSM Equations. Discret. Event Dyn. Syst. 18(1): 51-89 (2008) - [c212]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539 - [c211]Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton:
Merging nodes under sequential observability. DAC 2008: 540-545 - [c210]Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony:
Invariant-Strengthened Elimination of Dependent State Elements. FMCAD 2008: 1-9 - [c209]Alan Mishchenko, Robert K. Brayton:
Recording Synthesis History for Sequential Verification. FMCAD 2008: 1-8 - [c208]Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44 - [c207]Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang:
Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241 - [c206]Fan Mo, Robert K. Brayton:
Placement based multiplier rewiring for cell-based designs. ICCAD 2008: 430-433 - 2007
- [j50]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 240-253 (2007) - [c205]Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407 - [c204]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann:
On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605 - [c203]Michael L. Case, Alan Mishchenko, Robert K. Brayton:
Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172 - [c202]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187 - [c201]Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A new algorithm for the largest compositionally progressive solution of synchronous language equations. ACM Great Lakes Symposium on VLSI 2007: 441-444 - [c200]Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton:
Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361 - [c199]Fan Mo, Robert K. Brayton:
A simultaneous bus orientation and bused pin flipping algorithm. ICCAD 2007: 386-389 - [c198]Fan Mo, Robert K. Brayton:
Semi-detailed bus routing with variation reduction. ISPD 2007: 143-150 - [i2]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. CoRR abs/0710.4695 (2007) - [i1]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007) - 2006
- [j49]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - [j48]Alan Mishchenko, Robert K. Brayton:
A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 977-999 (2006) - [j47]Jie-Hong Roland Jiang, Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2674-2686 (2006) - [j46]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2894-2903 (2006) - [c197]Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515 - [c196]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535 - [c195]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49 - [c194]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton:
Factor cuts. ICCAD 2006: 143-150 - [c193]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén:
Improvements to combinational equivalence checking. ICCAD 2006: 836-843 - 2005
- [c192]Yinghua Li, Alex Kondratyev, Robert K. Brayton:
Gaining Predictability and Noise Immunity in Global Interconnects. ACSD 2005: 176-185 - [c191]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. DATE 2005: 412-417 - [c190]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423 - [c189]Yinghua Li, Alex Kondratyev, Robert K. Brayton:
Synthesis methodology for built-in at-speed testing. ICCAD 2005: 183-188 - [c188]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing structural bias in technology mapping. ICCAD 2005: 519-526 - 2004
- [j45]Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1020-1030 (2004) - [c187]Jie-Hong Roland Jiang, Robert K. Brayton:
Functional Dependency for Verification Reduction. CAV 2004: 268-280 - [c186]Fan Mo, Robert K. Brayton:
A timing-driven module-based chip design flow. DAC 2004: 67-70 - [c185]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
On breakable cyclic definitions. ICCAD 2004: 411-418 - [c184]Satrajit Chatterjee, Robert K. Brayton:
A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD 2004: 541-548 - 2003
- [j44]Jie-Hong Roland Jiang, Robert K. Brayton:
On the verification of sequential equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 686-697 (2003) - [j43]Fan Mo, Robert K. Brayton:
PLA-based regular structures and their synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 723-729 (2003) - [j42]Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton:
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) - [c183]Yunjian Jiang, Robert K. Brayton:
Don't cares in logic minimization of extended finite state machines. ASP-DAC 2003: 809-815 - [c182]Yunjian Jiang, Slobodan Matic, Robert K. Brayton:
Generalized cofactoring for logic function evaluation. DAC 2003: 155-158 - [c181]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757 - [c180]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. DATE 2003: 11154-11155 - [c179]Alan Mishchenko, Robert K. Brayton:
A Theory of Non-Deterministic Networks. ICCAD 2003: 709-717 - [c178]Fan Mo, Robert K. Brayton:
Fishbone: a block-level placement and routing scheme. ISPD 2003: 204-209 - 2002
- [j41]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. 21(2): 193-224 (2002) - [c177]Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. CODES 2002: 151-156 - [c176]Fan Mo, Robert K. Brayton:
River PLAs: a regular circuit structure. DAC 2002: 201-206 - [c175]Yunjian Jiang, Robert K. Brayton:
Software synthesis from synchronous specifications using logic simulation techniques. DAC 2002: 319-324 - [c174]Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton:
Using Problem Symmetry in Search Based Satisfiability Algorithms. DATE 2002: 134-141 - [c173]Fan Mo, Robert K. Brayton:
Whirlpool PLAs: a regular logic structure and their synthesis. ICCAD 2002: 543-550 - [c172]Alan Mishchenko, Robert K. Brayton:
Simplification of non-deterministic multi-valued networks. ICCAD 2002: 557-562 - [c171]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically constrained logic synthesis. ICCAD 2002: 679-686 - [c170]Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-179 - [c169]Fan Mo, Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS 2002: 7-12 - [c168]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - [c167]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. IWLS 2002: 45-50 - [c166]Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177 - [c165]Jie-Hong Roland Jiang, Robert K. Brayton:
On the Verification of Sequential Equivalence. IWLS 2002: 307-314 - [c164]Yunjian Jiang, Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS 2002: 327-332 - [c163]Alan Mishchenko, Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338 - [c162]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - 2001
- [j40]Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State-Space Exploration. Formal Methods Syst. Des. 18(2): 97-116 (2001) - [j39]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 249-265 (2001) - [c161]