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ORCIDFPGA 2020: Seaside, CA, USA
- Stephen Neuendorffer, Lesley Shannon:
FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020. ACM 2020, ISBN 978-1-4503-7099-8
Morning Tutorial Session
- Lana Josipovic
, Andrea Guerrieri, Paolo Ienne:
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. 1-10 - Kaspar Matas, Tuan La, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch:
Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond. 11-20
Invited Session: Security in FPGA Design and Application
- Lee W. Lerner:
Establishing Trust in Microelectronics. 21 - Jakub Szefer:
Thermal and Voltage Side and Covert Channels and Attacks in Cloud FPGAs. 22 - Patrick Koeberl:
Multi-tenant FPGA Security: Challenges and Opportunities. 23 - Steven McNeil:
FPGA / SoC Security: Arms Race in the Cloud. 24-25
Panel
- Andrew Putnam:
What To Do With Datacenter FPGAs Besides Deep Learning. 26
Session: Keynote I
- Mahesh A. Iyer:
Symbiosis in Action: Reconfigurable Architectures and EDA. 27-28
Session: High-Level Abstractions and Tools I
- Tuan D. A. Nguyen, Akash Kumar:
Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment. 29-39 - Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin:
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. 40-50 - Jiajie Li, Yuze Chi, Jason Cong:
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. 51-57 - Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, Jakub Szefer:
Fingerprinting Cloud FPGA Infrastructures. 58-64
Session: Applications I
- Yu Zou, Mingjie Lin:
Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization. 65-75 - Philippos Papaphilippou, Jiuxi Meng, Wayne Luk:
High-Performance FPGA Network Switch Architecture. 76-85 - Tanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz:
Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator. 86-96 - Qiuyue Sun, Amir Taherin, Yawo Siatitse, Yuhao Zhu:
Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design. 97-103 - Anish Singhani, Alexander Morrow:
Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sailing. 104-110
Session: Deep Learning I
- Vladimir Rybalkin, Norbert Wehn:
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. 111-121 - Yunxuan Yu, Tiandong Zhao, Kun Wang, Lei He:
Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks. 122-132 - Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
End-to-End Optimization of Deep Learning Applications. 133-139
Session: FPGA Architecture
- Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov:
Architectural Enhancements in Intel® Agilex™ FPGAs. 140-149 - Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. 150-160 - Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. 161-171
Invited Panel
- Raymond X. Nijssen:
FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know It. 172
Session: Keynote II
- Vinod Kathail:
Xilinx Vitis Unified Software Platform. 173-174
Session: High-Level Abstractions and Tools II
- Sameh Attia, Vaughn Betz:
StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging. 175-185 - Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. 186-196 - Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic:
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. 197-203 - Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic:
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. 204-210
Session: Applications II
- Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka:
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. 211-221 - Han Chen, Sergey Madaminov, Michael Ferdman, Peter A. Milder:
FPGA-Accelerated Samplesort for Large Data Sets. 222-232 - Zhenhao He, Zeke Wang, Gustavo Alonso:
BiS-KM: Enabling Any-Precision K-Means on FPGAs. 233-243 - Johannes de Fine Licht, Grzegorz Kwasniewski, Torsten Hoefler:
Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis. 244-254
Session: Deep Learning II
- Hanqing Zeng, Viktor K. Prasanna:
GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms. 255-265 - Yue Niu, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna:
Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration. 266-276
Session: High-Level Synthesis and Tools
- Yann Herklotz, John Wickerson:
Finding and Understanding Bugs in FPGA Synthesis Tools. 277-287 - Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. 288-298 - Jiantong Jiang, Zeke Wang, Xue Liu, Juan Gómez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu:
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs. 299-309
Poster Session I
- Samuel Dewan, Paulo Garcia:
Programming Abstractions for Configurable Hardware: Survey and Research Directions. 310 - Changsu Kim, Yongwoo Lee, Shinnung Jeong, Wen Wang, Jakub Szefer, Hanjun Kim:
Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms. 310 - Endri Bezati, Mahyar Emami, James R. Larus:
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. 310 - Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. 311 - Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim:
Productive Hardware Designs using Hybrid HLS-RTL Development. 311 - Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Unleashing the Power of FPGAs as Programmable Switches. 311 - Parnian Mokri, Maziar Amiraskari, Yuelin Liu, Mark Hempstead:
Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree. 312 - Oron Port, Yoav Etsion:
Hardware Description Beyond Register-Transfer Level Languages. 312 - Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia:
MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. 312 - Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai:
A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. 313 - Yang Yang, Chao Wang, Lei Gong, Xuehai Zhou:
ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAs. 313 - Oscar Rahnama, Tommaso Cavallari, Philip H. S. Torr, Stuart Golodetz:
Scalable FPGA Median Filtering using Multiple Efficient Passes. 313 - Ke He, Bo Liu, Yu Zhang, Andrew Ling, Dian Gu:
FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10. 314
Poster Session II
- Juan Escobedo, Mingjie Lin:
DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils. 315 - Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang:
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. 315 - Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. 315 - Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar:
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. 316 - Jincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang, Huazhong Yang:
INCAME: INterruptible CNN Accelerator for Multi-robot Exploration. 316 - Tianyu Zhang, Tiantian Han, Lu Tian, Yi Li, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott, Yi Shan:
LPAC: A Low-Precision Accelerator for CNN on FPGAs. 316 - Shulin Zeng, Guohao Dai, Kai Zhong, Hanbo Sun, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud. 317 - Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle:
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. 317 - Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic:
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. 317 - Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar:
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. 318 - Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong:
CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time. 318 - Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He:
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration. 318 - Ruihao Li, Ke Liu, Mengying Zhao, Zhaoyan Shen, Xiaojun Cai, Zhiping Jia:
Maximizing CNN Throughput on FPGA Clusters. 319 - Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk:
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. 319 - Rene Miedema, Georgios Smaragdos, Mario Negrello, Zaid Al-Ars, Matthias Möller, Christos Strydis:
Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations. 319 - Mathew Hall, Vaughn Betz:
HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs. 320 - Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding:
FTDL: An FPGA-tailored Architecture for Deep Learning Systems. 320
Poster Session III
- Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim:
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping. 321 - Atsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano:
Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA. 321 - Yun Zhou, Dries Vercruyce, Dirk Stroobandt:
On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing. 321 - Martin Langhammer, Sergey Gribok, Gregg Baeckler:
High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA. 322 - Stephen M. Williams, Mingjie Lin:
Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs. 322 - Ang Li, David Wentzlaff:
Cycle-Free FPGA Routing Graphs. 322 - Rupesh S. Shelar:
An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops. 323 - Rachit Rajat, Yuan Meng, Sanmukh R. Kuppannagari, Ajitesh Srivastava, Viktor K. Prasanna, Rajgopal Kannan:
QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators. 323 - Aman Arora, Zhigang Wei, Lizy K. John:
The Case for Hard Matrix Multiplier Blocks in an FPGA. 323 - Nils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk:
Performance Portable FPGA Design. 324 - Tanvir Ahmed, Johannes Maximilian Kühn:
Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators. 324 - Nikolaos Alachiotis, Panagiotis Skrimponis, Emmanouil Pissadakis, Sundeep Rangan, Dionisios N. Pnevmatikatos:
Near-memory Acceleration for Scalable Phylogenetic Inference. 324 - Yufan Zhang, Zhengjie Li, Jian Wang, Jinmei Lai:
FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. 325 - Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
INTB: A New FPGA Interconnect Model for Architecture Exploration. 325 - Taesu Kim, Daehyun Ahn, Jae-Joon Kim:
V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. 326 - Unai Martinez-Corral, Guillermo Callaghan, Konstantinos Iordanou, Cosmin Gorgovan, Koldo Basterretxea, Mikel Luján:
DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs. 326
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