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2020 – today
- 2024
[c10]Andy Huang
, Zhiming Wang, Wenhui Ni, Sheng Chen, Nithin George:
CodePin: An Instrumentation-Based Debug Tool of SYCLomatic. IWOCL 2024: 16:1-16:2- 2020
- [c9]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9
2010 – 2019
- 2017
- [j2]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [j1]João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva:
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5: 14600-14615 (2017) - 2016
- [b1]Nithin George:
FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages. EPFL, Switzerland, 2016 - [c8]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c7]Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180 - 2015
- [c6]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM 2015: 97 - [c5]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL 2015: 1-8 - [c4]Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8 - 2014
- [c3]Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. FPL 2014: 1-8 - 2013
- [c2]Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. FPT 2013: 120-127 - 2012
- [c1]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264
Coauthor Index
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