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ORCIDRainer Leupers
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- affiliation: RWTH Aachen University, Germany
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2020 – today
- 2024
[j51]Chandan Kumar Jha
, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler:
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024)- [c256]José Cubero-Cascante, Arunkumar Vaidyanathan, Rebecca Pelke, Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph:
A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars. AICAS 2024: 537-538 - [c255]Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach, Lukas Jünger, Rainer Leupers:
The Optimal Quantum of Temporal Decoupling. ASPDAC 2024: 686-691 - [c254]Felix Staudigl, Jan Philipp Thoma, Christian Niesler, Karl J. X. Sturm, Rebecca Pelke, Dominik Germek, Jan Moritz Joseph, Tim Güneysu, Lucas Davi, Rainer Leupers:
NVM-Flip: Non-Volatile-Memory BitFlips on the System Level. SAT-CPS@CODASPY 2024: 11-20 - [c253]Nils Bosbach, Niko Zurstraßen, Rebecca Pelke, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. DAC 2024: 73:1-73:6 - [c252]Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. DATE 2024: 1-6 - [c251]Leon Happek, Jen-Tse Huang, Alejandro Garcia Gener, Rainer Leupers, Melvin Galicia:
Spiking Neural Networks for Signal Classification with Digital and Analog Neuromorphic Systems: A Comparative Study. IJCNN 2024: 1-7 - [c250]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. LATS 2024: 1-6 - [c249]Lorenzo Pfeifer, M. Gross, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators. LATS 2024: 1-4 - [c248]Nils Bosbach, Alwalid Salama, Lukas Jünger, Mark Burton, Niko Zurstraßen, Rebecca Pelke, Rainer Leupers:
NQC²: A Non-Intrusive QEMU Code Coverage Plugin. RAPIDO@HiPEAC 2024: 16-21 - [i36]Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. CoRR abs/2401.07671 (2024) - [i35]Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR abs/2401.17819 (2024) - [i34]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Leticia Bolzani Poehls, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. CoRR abs/2403.13655 (2024) - [i33]Lennart M. Reimann, Yadu Madhukumar Variyar, Lennet Huelser, Chiara Ghinami, Dominik Germek, Rainer Leupers:
Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction. CoRR abs/2408.04976 (2024) - 2023
- [j50]Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant:
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135: 102801 (2023) - [c247]Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms. CODES+ISSS 2023: 42-43 - [c246]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS 2023: 44-45 - [c245]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC 2023: 1-6 - [c244]Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer:
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE 2023: 1-6 - [c243]Niko Zurstraßen, José Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers:
par-gem5: Parallelizing gem5's Atomic Mode. DATE 2023: 1-6 - [c242]Nils Bosbach, Lukas Jünger, Rebecca Pelke, Niko Zurstraßen, Rainer Leupers:
Entropy-Based Analysis of Benchmarks for Instruction Set Simulators. DroneSE/RAPIDO@HiPEAC 2023: 54-59 - [c241]Niko Zurstraßen, Nils Bosbach, Jan Moritz Joseph, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Efficient RISC-V-on-x64 Floating Point Simulation. ICCD 2023: 558-565 - [c240]Melvin Estuardo Galicia, Ibrahim Jimale Osman, Christian Owusu-Afriyie, Rainer Leupers:
"S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar Arrays. ICONS 2023: 41:1-41:8 - [c239]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS 2023: 1-4 - [c238]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers:
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS 2023: 1-6 - [c237]Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant:
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH 2023: 30:1-30:7 - [c236]Melvin Galicia, Leon Happek, Magnus Balzer, Rainer Leupers:
Frequency and noise characterization for baseband signal processing on neuromorphic circuits. NEWCAS 2023: 1-5 - [c235]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS 2023: 1-5 - [c234]Lennart M. Reimann, Felix Staudigl, Rainer Leupers:
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. NEWCAS 2023: 1-5 - [c233]José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph:
parti-gem5: gem5's Timing Mode Parallelised. SAMOS 2023: 177-192 - [c232]Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Mapping of CNNs on multi-core RRAM-based CIM architectures. VLSI-SoC 2023: 1-6 - [c231]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC 2023: 1-6 - [i32]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR abs/2302.07655 (2023) - [i31]Lennart M. Reimann, Felix Staudigl, Rainer Leupers:
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. CoRR abs/2304.05682 (2023) - [i30]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR abs/2304.05686 (2023) - [i29]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR abs/2308.02400 (2023) - [i28]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR abs/2308.02694 (2023) - [i27]José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph:
parti-gem5: gem5's Timing Mode Parallelised. CoRR abs/2308.09445 (2023) - [i26]Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Mapping of CNNs on multi-core RRAM-based CIM architectures. CoRR abs/2309.03805 (2023) - 2022
- [j49]Felix Staudigl, Farhad Merchant, Rainer Leupers:
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. IEEE Des. Test 39(2): 90-99 (2022) - [j48]Niko Zurstraßen, Lukas Jünger, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators. Int. J. Parallel Program. 50(2): 295-318 (2022) - [j47]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1716-1729 (2022) - [c230]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS 2022: 174-177 - [c229]Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers:
Designing ML-resilient locking at register-transfer level. DAC 2022: 769-774 - [c228]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Letícia Maria Bolzani Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser:
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c227]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c226]Lukas Jünger, Simon Winther, Rainer Leupers:
X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems. DSD 2022: 142-148 - [c225]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. FPL 2022: 334-341 - [c224]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST 2022: 61-64 - [c223]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. ISQED 2022: 1-6 - [c222]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS 2022: 1-4 - [c221]Sebastian Birke, Bjoern Hartmann, Dominik Auras, Markus Wloka, Gerd Ascheid, Rainer Leupers:
Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications. NorCAS 2022: 1-7 - [c220]Lukas Jünger, Antonios Salios, Peter Blöcher, Rainer Leupers:
Virtual Platform Acceleration through Userspace Host Execution. SOCC 2022: 1-6 - [c219]Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. VLSI-SoC 2022: 1-6 - [c218]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC 2022: 1-6 - [i25]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR abs/2202.12085 (2022) - [i24]Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers:
Designing ML-Resilient Locking at Register-Transfer Level. CoRR abs/2203.05399 (2022) - [i23]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR abs/2204.01501 (2022) - [i22]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. CoRR abs/2206.11613 (2022) - [i21]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. CoRR abs/2207.10526 (2022) - [i20]Nils Bosbach, Lukas Jünger, Jan Moritz Joseph, Rainer Leupers:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. CoRR abs/2207.11036 (2022) - [i19]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR abs/2208.04769 (2022) - [i18]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR abs/2211.16891 (2022) - 2021
- [j46]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17(3): 30:1-30:26 (2021) - [j45]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs. IEEE Open J. Circuits Syst. 2: 3-15 (2021) - [c217]Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck:
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC 2021: 197-203 - [c216]Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers:
Optimizing Temporal Decoupling using Event Relevance. ASP-DAC 2021: 331-337 - [c215]Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer:
Nano Security: From Nano-Electronics to Secure Systems. DATE 2021: 1334-1339 - [c214]Milan Copic, Rainer Leupers, Gerd Ascheid:
Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism. DSD 2021: 418-425 - [c213]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD 2021: 603-607 - [c212]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED 2021: 60-66 - [c211]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. ISQED 2021: 463-468 - [c210]Jan Moritz Joseph, Murat Sezgin Baloglu, Yue Pan, Rainer Leupers, Lennart Bamberg:
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. NOCS 2021: 15-20 - [c209]Lukas Jünger, Alexander Belke, Rainer Leupers:
Software-defined Temporal Decoupling in Virtual Platforms. SoCC 2021: 40-45 - [c208]Melvin Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, Sander Stuijk, Henk Corporaal, Rainer Leupers:
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators. SoCC 2021: 236-241 - [c207]Dominik Sisejkovic, Rainer Leupers:
Trustworthy Hardware Design with Logic Locking. VLSI-SoC 2021: 1-2 - [c206]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC 2021: 1-6 - [c205]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID 2021: 270-275 - [c204]Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers:
An Investigation on Inherent Robustness of Posit Data Representation. VLSID 2021: 276-281 - [i17]Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers:
An Investigation on Inherent Robustness of Posit Data Representation. CoRR abs/2101.01416 (2021) - [i16]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR abs/2101.05591 (2021) - [i15]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. CoRR abs/2101.06665 (2021) - [i14]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR abs/2107.01915 (2021) - [i13]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR abs/2107.08695 (2021) - [i12]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR abs/2109.02379 (2021) - [i11]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - [i10]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. CoRR abs/2112.13157 (2021) - 2020
- [j44]Jure Vreca, Karl J. X. Sturm, Ernest Gungl, Farhad Merchant, Paolo Bientinesi, Rainer Leupers, Zmago Brezocnik:
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access 8: 165913-165926 (2020) - [j43]Milan Copic, Rainer Leupers, Gerd Ascheid:
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling. Integr. 70: 10-20 (2020) - [c203]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. ARCS 2020: 56-68 - [c202]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß:
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c201]Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar:
Next Generation Arithmetic for Edge Computing. DATE 2020: 1357-1365 - [c200]Lukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann:
ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms. DATE 2020: 1508-1513 - [c199]Milan Copic, Rainer Leupers, Gerd Ascheid:
Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables. ISSRE 2020: 127-137 - [c198]Lukas Jünger, Niko Zurstraßen, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX: A Generic Analytical Model for Deep Learning Accelerators. SAMOS 2020: 36-51 - [c197]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß:
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i9]Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers:
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR abs/2006.00364 (2020) - [i8]Andreas Bytyn, René Ahlsdorf, Rainer Leupers, Gerd Ascheid:
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect. CoRR abs/2006.12274 (2020) - [i7]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020) - [i6]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j42]Gereon Führ, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. IEEE Embed. Syst. Lett. 11(3): 93-96 (2019) - [j41]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. Integr. 69: 50-61 (2019) - [c196]Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers:
Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS 2019: 121-124 - [c195]Milan Copic, Rainer Leupers, Gerd Ascheid:
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. ASP-DAC 2019: 603-608 - [c194]Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen:
A heuristic for multi objective software application mappings on heterogeneous MPSoCs. ASP-DAC 2019: 609-614 - [c193]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS 2019: 1-6 - [c192]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI 2019: 27-32 - [c191]Sebastian Birke, Dominik Auras, Tobias Piwczyk, Robin Mahlke, Nikolas Alberti, Rainer Leupers, Gerd Ascheid:
VLSI Architectures for ORVD Trellis based MIMO Detection. ICNC 2019: 983-989 - [c190]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ISCAS 2019: 1-5 - [c189]Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Fast SystemC Processor Models with Unicorn. RAPIDO 2019: 2:1-2:6 - [c188]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC 2019: 424-425 - [c187]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer:
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT 2019: 1-4 - [c186]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID 2019: 64-69 - [c185]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSID 2019: 431-436 - [i5]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. CoRR abs/1904.05106 (2019) - 2018
- [c184]Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping. APCCAS 2018: 532-535 - [c183]Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress. CODES+ISSS 2018: 13 - [c182]Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann:
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. DATE 2018: 281-284 - [c181]Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers:
Parameterized Posit Arithmetic Hardware Generator. ICCD 2018: 334-341 - [c180]Dominik Auras, Sebastian Birke, Rainer Leupers, Gerd Ascheid:
Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection. ICNC 2018: 315-321 - [c179]Robert Lajos Bücs, Marcel Heistermann, Rainer Leupers, Gerd Ascheid:
Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach. ICVES 2018: 1-8 - [c178]Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers, Gerd Ascheid:
VLSI implementation of channel estimation for millimeter wave beamforming training. LASCAS 2018: 1-4 - [c177]Koen De Bosschere, Rainer Leupers:
HiPEAC compilation architecture. MECO 2018: 13 - [c176]Gereon Onnebrink, Rainer Leupers, Gerd Ascheid:
ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models. RAPIDO 2018: 1:1-1:6 - [c175]Dominik Sisejkovic, Rainer Leupers, Gerd Ascheid, Simon Metzner:
A Unifying logic encryption security metric. SAMOS 2018: 179-186 - [c174]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping. SMARTGREENS/VEHITS (Selected Papers) 2018: 181-201 - [c173]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. VEHITS 2018: 59-69 - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j40]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. Int. J. Parallel Program. 45(6): 1592-1624 (2017) - [c172]Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick:
Multi-grained performance estimation for MPSoC compilers: work-in-progress. CASES 2017: 14:1-14:2 - [c171]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick:
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. DATE 2017: 1237-1240 - [c170]María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers:
Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition. PARMA-DITAM@HiPEAC 2017: 13-18 - [c169]Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid:
VLSI implementation of LS-SVM training and classification using entropy based subset-selection. ISCAS 2017: 1-4 - [c168]Robert Lajos Bücs, Juan Sebastian Reyes Aristizabal, Rainer Leupers, Gerd Ascheid:
Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment. ITSC 2017: 1-8 - [c167]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models. RAPIDO 2017: 2 - [c166]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Extraction of recursion level parallelism for embedded multicore systems. SAMOS 2017: 154-162 - [c165]Gereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn:
DVFS-enabled power-performance trade-off in MPSoC SW application mapping. SAMOS 2017: 196-202 - [p4]Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng:
MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign 2017: 917-949 - 2016
- [j39]Andres Goens, Jerónimo Castrillón, Maximilian Odendahl, Rainer Leupers:
An optimal allocation of memory buffers for complex multicore platforms. J. Syst. Archit. 66-67: 69-83 (2016) - [j38]Pier Stanislao Paolucci, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula:
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. 69: 29-53 (2016) - [j37]Daniel Günther, Rainer Leupers, Gerd Ascheid:
A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1283-1294 (2016) - [j36]Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs. ACM Trans. Embed. Comput. Syst. 16(1): 7:1-7:25 (2016) - [j35]Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model. ACM Trans. Embed. Comput. Syst. 16(1): 26:1-26:26 (2016) - [j34]Jan Henrik Weinstock, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Parallel SystemC Simulation for ESL Design. ACM Trans. Embed. Comput. Syst. 16(1): 27:1-27:25 (2016) - [j33]Daniel Günther, Rainer Leupers, Gerd Ascheid:
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 567-577 (2016) - [c164]Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu:
Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting. ARCS 2016: 277-289 - [c163]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo:
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. DAC 2016: 49:1-49:6 - [c162]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann:
SystemC-link: Parallel SystemC simulation using time-decoupled segments. DATE 2016: 493-498 - [c161]Rainer Leupers:
Technology Transfer in computing systems: The TETRACOM approach. DATE 2016: 834-837 - [c160]Daniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid:
Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing. DATE 2016: 1028-1029 - [c159]Gereon Onnebrink, Stefan Schürmans, Florian Walbroel, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, YwhPyng Harn:
Black box power estimation for digital signal processors using virtual platforms. RAPIDO@HiPEAC 2016: 6:1-6:6 - [c158]Dominik Auras, Sebastian Birke, Tobias Piwczyk, Rainer Leupers, Gerd Ascheid:
A flexible MCMC detector ASIC. ISOCC 2016: 285-286 - [c157]Dominik Auras, Rainer Leupers, Gerd Ascheid:
ORVD-Trellis based MIMO detection. NEWCAS 2016: 1-4 - [c156]Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid:
Concurrent memory subsystem and application optimization for ASIP design. SAMOS 2016: 1-10 - [c155]Maria H. Rodriguez Blanco, Georg Reinke, Gerd Ascheid, Rainer Leupers:
Automatic recognition of computational kernels for platform-dependent code optimizations. SAMOS 2016: 11-20 - [c154]Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Stefan Schürmans:
Black box ESL power estimation for loosely-timed TLM models. SAMOS 2016: 366-371 - 2015
- [j32]Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers:
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. ACM Trans. Reconfigurable Technol. Syst. 8(3): 17:1-17:16 (2015) - [j31]Xiaolin Chen, Andreas Minwegen, Bilal Syed Hussain, Anupam Chattopadhyay, Gerd Ascheid, Rainer Leupers:
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2173-2186 (2015) - [c153]Miguel Angel Aguilar, Rainer Leupers:
Unified Identification of Multiple Forms of Parallelism in Embedded Applications. PACT 2015: 482-483 - [c152]Luis Gabriel Murillo, Robert Lajos Bücs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid:
SWAT: Assertion-based debugging of concurrency issues at system level. ASP-DAC 2015: 600-605 - [c151]Ayman Tarakji, Marwan Hassani, Lyubomir Georgiev, Thomas Seidl, Rainer Leupers:
Parallel Density-Based Stream Clustering Using a Multi-user GPU Scheduler. BDAS 2015: 343-360 - [c150]Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers:
Multi/many-core programming: where are we standing? DATE 2015: 1708-1717 - [c149]Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann:
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. FDL 2015: 49-56 - [c148]Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl:
Extraction of Kahn Process Networks from While Loops in Embedded Software. HPCC/CSS/ICESS 2015: 1078-1085 - [c147]Cosmin Cernazanu-Glavan, Marius Marcu, Alexandru Amaricai, Stefan Fedeac, Madalin Ghenea, Zheng Wang, Anupam Chattopadhyay, Jan Weinstock, Rainer Leupers:
Direct FPGA-based power profiling for a RISC processor. I2MTC 2015: 1578-1583 - [c146]Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Tomas Henriksson:
Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms. IPDPS Workshops 2015: 1119-1124 - [c145]Ayman Tarakji, Lukas Börger, Rainer Leupers:
A comparative investigation of device-specific mechanisms for exploiting HPC accelerators. GPGPU@PPoPP 2015: 1-12 - [c144]Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig 2015: 1-8 - [c143]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Parallelism extraction in embedded software for android devices. SAMOS 2015: 9-17 - [c142]Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
Deterministic event-based control of Virtual Platforms for MPSoC software debugging. SAMOS 2015: 348-353 - [c141]Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
ESL power estimation using virtual platforms with black box processor models. SAMOS 2015: 354-359 - [c140]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Parallel SystemC simulation for ESL design using flexible time decoupling. SAMOS 2015: 378-383 - [c139]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias:
A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms. SCOPES 2015: 76-79 - [c138]Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid:
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. SCOPES 2015: 84-87 - [c137]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator. SCOPES 2015: 129-132 - [c136]Ayman Tarakji, Alexander Gladis, Tarek Anwar, Rainer Leupers:
Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling. TrustCom/BigDataSE/ISPA (3) 2015: 45-52 - [c135]Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. VLSI-SoC 2015: 337-342 - 2014
- [j30]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
A compiler infrastructure for embedded heterogeneous MPSoCs. Parallel Comput. 40(2): 51-68 (2014) - [j29]Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Andreas Hoffmann:
legaSCi: Legacy SystemC Model Integration into Parallel Simulators. ACM Trans. Embed. Comput. Syst. 13(5s): 165:1-165:24 (2014) - [c134]Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue:
A flexible ASIP architecture for connected components labeling in embedded vision applications. DATE 2014: 1-6 - [c133]Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson:
Technology transfer towards Horizon 2020. DATE 2014: 1 - [c132]Luis Gabriel Murillo, Simon Wawroschek, Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
Automatic detection of concurrency bugs through event ordering constraints. DATE 2014: 1-6 - [c131]Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson:
Optimized buffer allocation in multicore platforms. DATE 2014: 1-6 - [c130]Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto:
Time-decoupled parallel SystemC simulation. DATE 2014: 1-4 - [c129]Dominik Auras, Dominik Rieth, Rainer Leupers, Gerd Ascheid:
VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract. ACM Great Lakes Symposium on VLSI 2014: 71-72 - [c128]Dominik Auras, Rainer Leupers, Gerd H. Ascheid:
A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture. ICC 2014: 4722-4728 - [c127]Benjamin Ries, Walter Unger, Maximilian Odendahl, Rainer Leupers:
A heuristic for logical data buffer allocation in multicore platforms. IPCCC 2014: 1-2 - [c126]Dominik Auras, Rainer Leupers, Gerd Ascheid:
Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors. ISCAS 2014: 1018-1021 - [c125]Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock:
EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. ISPA 2014: 182-189 - [c124]Daniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems. ISSoC 2014: 1-7 - [c123]Dominik Auras, Rainer Leupers, Gerd Ascheid:
A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture. ISVLSI 2014: 41-47 - [c122]Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Pre-architectural performance estimation for ASIP design based on abstract processor models. ICSAMOS 2014: 133-140 - [c121]Stefan Schürmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Improving ESL power models using switching activity information from timed functional models. SCOPES 2014: 89-97 - [c120]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers. VLSI-SoC 2014: 1-6 - [c119]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm. VLSI-SoC (Selected Papers) 2014: 149-169 - 2013
- [j28]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid:
Automatic Calibration of Streaming Applications for Software Mapping Exploration. IEEE Des. Test 30(3): 49-58 (2013) - [j27]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. Int. J. Embed. Real Time Commun. Syst. 4(1): 64-84 (2013) - [j26]Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. IEEE Trans. Ind. Informatics 9(1): 527-545 (2013) - [c118]Massimiliano Donati, Sergio Saponara, Luca Fanucci, Walter Errico, Annamaria Colonna, Giuseppe Piscopiello, Giovanni Tuccio, Franco Bigongiari, Maximilian Odendahl, Rainer Leupers, Antonio Spada, Vincenzo Pii, Elena Cordiviola, Francesco Nuzzolo, Frederic Reiter:
A New Space Digital Signal Processor Design. ApplePies 2013: 51-60 - [c117]Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang:
Creation of ESL power models for communication architectures using automatic calibration. DAC 2013: 58:1-58:58 - [c116]Weihua Sheng, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform. HPCC/EUC 2013: 1745-1750 - [c115]Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Thorsten Grötker:
legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators. IPDPS Workshops 2013: 2188-2193 - [c114]Maximilian Odendahl, Jerónimo Castrillón, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Split-cost communication model for improved MPSoC application mapping. ISSoC 2013: 1-8 - [c113]Daniel Günther, Rainer Leupers, Gerd Ascheid:
Mapping of MIMO Receiver Algorithms onto Application-Specific Multi-Core Platforms. ISWCS 2013: 1-5 - [c112]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
A compiler infrastructure for embedded heterogeneous MPSoCs. PMAM 2013: 1-10 - [c111]Juan Fernando Eusse, Christopher Williams, Rainer Leupers:
CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design. ReCoSoC 2013: 1-8 - [c110]Sergio Saponara, Massimiliano Donati, Luca Fanucci, Maximilian Odendahl, Rainer Leupers, Walter Errico:
DSPACE hardware architecture for on-board real-time image/video processing in European space missions. Real-Time Image and Video Processing 2013: 86560D - [p3]Rainer Leupers, Weihua Sheng, Jerónimo Castrillón:
Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems 2013: 1215-1257 - [e2]Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala:
Handbook of Signal Processing Systems. Springer 2013, ISBN 978-1-4614-6858-5 [contents] - [i3]Pier Stanislao Paolucci, Iuliana Bacivarov, Gert Goossens, Rainer Leupers, Frédéric Rousseau, Christoph Schumacher, Lothar Thiele, Piero Vicini:
EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment. CoRR abs/1305.1459 (2013) - 2012
- [c109]Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid:
Synchronization for hybrid MPSoC full-system simulation. DAC 2012: 121-126 - [c108]Jerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid:
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. DAC 2012: 1266-1271 - [c107]Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid:
Hybrid simulation for extensible processor cores. DATE 2012: 288-291 - [c106]Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel:
Virtual platforms: Breaking new grounds. DATE 2012: 685-690 - [c105]Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid:
SCandal: SystemC Analysis for Nondeterminism Anomalies. FDL (Selected Papers) 2012: 69-88 - [c104]Christoph Schumacher, Jan Weinstock, Rainer Leupers, Gerd Ascheid:
Scandal: Systemc analysis for nondeterminism anomalies. FDL 2012: 112-119 - [c103]Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators. HLDVT 2012: 124-131 - [c102]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Application-aware spinlock control using a hardware scheduler in MPSoC platforms. ISSoC 2012: 1-6 - [c101]Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid:
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. MCSoC 2012: 51-58 - [c100]Anastasia Stulova, Rainer Leupers, Gerd Ascheid:
Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs. ICSAMOS 2012: 144-151 - [c99]Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS 2012: 278-285 - 2011
- [j25]Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A retargetable framework for compiler/architecture co-development. Des. Autom. Embed. Syst. 15(3-4): 311-342 (2011) - [j24]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers:
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. Int. J. Embed. Real Time Commun. Syst. 2(3): 1-20 (2011) - [j23]Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp, Andreas Hoffmann:
Checkpointing SystemC-Based Virtual Platforms. Int. J. Embed. Real Time Commun. Syst. 2(4): 21-37 (2011) - [j22]Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee, Hanno Scharwächter, Rainer Leupers:
Fast graph-based instruction selection for multi-output instructions. Softw. Pract. Exp. 41(6): 717-736 (2011) - [c98]Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen:
Virtual Manycore platforms: Moving towards 100+ processor cores. DATE 2011: 715-720 - [c97]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid:
Automatic calibration of streaming applications for software mapping exploration. SoC 2011: 136-142 - [c96]Jerónimo Castrillón, Weihua Sheng, Rainer Leupers:
Trends in embedded software synthesis. ICSAMOS 2011: 347-354 - [c95]Felix Engel, Rainer Leupers, Gerd Ascheid, Max Ferger, Marcel Beemster:
Enhanced structural analysis for C code reconstruction from IR code. SCOPES 2011: 21-27 - 2010
- [j21]David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Automatic Generation of Memory Interfaces for ASIPs. Int. J. Embed. Real Time Commun. Syst. 1(3): 1-23 (2010) - [j20]Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Analytical and Simulation-based Design Space Exploration of Software Defined Radios. Int. J. Parallel Program. 38(3-4): 303-321 (2010) - [j19]Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 706-710 (2010) - [c94]Rainer Leupers, Jerónimo Castrillón:
MPSoC programming using the MAPS compiler. ASP-DAC 2010: 897-902 - [c93]Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann:
parSC: synchronous parallel systemc simulation on multi-core host architectures. CODES+ISSS 2010: 241-246 - [c92]Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE 2010: 753-758 - [c91]Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki:
Cool MPSoC programming. DATE 2010: 1488-1493 - [c90]Stefan Schürmans, Elias Weingärtner, Torsten Kempf, Gerd Ascheid, Klaus Wehrle, Rainer Leupers:
Towards Network Centric Development of Embedded Systems. ICC 2010: 1-6 - [c89]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. SoC 2010: 163-168 - [c88]Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) 2010: 65-79 - [c87]Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI 2010: 494-499 - [c86]Rainer Leupers:
System level MPSoC design: a bright future for compiler technology? SCOPES 2010: 9 - [p2]Rainer Leupers, Weihua Sheng, Jerónimo Castrillón:
Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems 2010: 639-678 - [e1]Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala:
Handbook of Signal Processing Systems. Springer 2010, ISBN 978-1-4419-6344-4 [contents]
2000 – 2009
- 2009
- [j18]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated verification approach during ADL-driven processor design. Microelectron. J. 40(7): 1111-1123 (2009) - [j17]Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A SIMD optimization framework for retargetable compilers. ACM Trans. Archit. Code Optim. 6(1): 2:1-2:27 (2009) - [c85]Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20 - [c84]Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS 2009: 305-314 - [c83]Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl:
Programming MPSoC platforms: Road works ahead! DATE 2009: 1584-1589 - [c82]Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid:
Task management in MPSoCs: An ASIP approach. ICCAD 2009: 587-594 - [c81]David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay:
Automatic generation of memory interfaces. SoC 2009: 77-82 - [c80]Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp:
A checkpoint/restore framework for systemc-based virtual platforms. SoC 2009: 161-167 - [c79]Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS 2009: 204-214 - [c78]David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI 2009: 309-314 - [c77]Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design 2009: 281-286 - [i2]Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding. CoRR abs/0910.3427 (2009) - [i1]David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr:
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. 2009: 56 (2009) - 2008
- [j16]Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr:
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. 3(3): 109-118 (2008) - [j15]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr:
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. 3(3): 150-159 (2008) - [j14]Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. 3(3): 25-38 (2008) - [j13]Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. 7(4): 40:1-40:31 (2008) - [j12]Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid:
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1281-1294 (2008) - [c76]Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Multiprocessor performance estimation using hybrid simulation. DAC 2008: 325-330 - [c75]Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda:
MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759 - [c74]Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE 2008: 1334-1339 - [c73]Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh:
Retargetable Code Optimization for Predicated Execution. DATE 2008: 1492-1497 - [c72]Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle:
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. DATE 2008 - 2007
- [b6]Oliver Schliebusch, Heinrich Meyr, Rainer Leupers:
Optimized ASIP synthesis from architecture description language models. RWTH Aachen University, Germany, Kluwer 2007, ISBN 978-1-4020-5685-7, pp. I-XIV, 1-193 - [j11]Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embed. Comput. Syst. 6(2): 12 (2007) - [c71]Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A fast and generic hybrid simulation approach using C virtual machine. CASES 2007: 3-12 - [c70]Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
HySim: a fast simulation framework for embedded software development. CODES+ISSS 2007: 75-80 - [c69]Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr:
A code-generator generator for multi-output instructions. CODES+ISSS 2007: 131-136 - [c68]Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors. DATE 2007: 319-324 - [c67]Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE 2007: 1349-1354 - [c66]Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD 2007: 166-171 - [c65]Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194 - 2006
- [b5]Tim Kogel, Rainer Leupers, Heinrich Meyr:
Integrated system-level modeling of network-on-chip enabled multi-processor platforms. RWTH Aachen University, Germany, Kluwer 2006, ISBN 978-1-4020-4825-8, pp. I-XIV, 1-199 - [j10]Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers:
Offset assignment using simultaneous variable coalescing. ACM Trans. Embed. Comput. Syst. 5(4): 864-883 (2006) - [j9]Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J. VLSI Signal Process. 43(2-3): 235-246 (2006) - [c64]Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren:
Retargetable code optimization with SIMD instructions. CODES+ISSS 2006: 148-153 - [c63]Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini:
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. CODES+ISSS 2006: 167-172 - [c62]Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia:
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226 - [c61]Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238 - [c60]Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE 2006: 468-473 - [c59]Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey:
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. DATE 2006: 581-586 - [c58]Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605 - [c57]Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE 2006: 919-924 - [c56]Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini:
An integrated open framework for heterogeneous MPSoC design space exploration. DATE 2006: 1145-1150 - [c55]Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Memory Access Micro-Profiling for ASIP Design. DELTA 2006: 255-262 - [c54]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118 - 2005
- [c53]Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP 2005: 154-160 - [c52]Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 - [c51]Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel:
Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 - [c50]Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Fine-grained application source code profiling for ASIP design. DAC 2005: 329-334 - [c49]Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 - [c48]Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models. DATE 2005: 1150-1155 - [c47]Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171 - [p1]Rainer Leupers, Gerd Ascheid:
Digital Signal Processors. Handbook of Networked and Embedded Control Systems 2005: 279-294 - 2004
- [j8]Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1625-1639 (2004) - [c46]Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis, Rainer Leupers:
Compiler based exploration of DSP energy savings by SIMD operations. ASP-DAC 2004: 838-841 - [c45]Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr:
A novel approach for flexible and consistent ADL-driven ASIP design. DAC 2004: 717-722 - [c44]Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160 - [c43]Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 - [c42]Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 - [c41]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 - [c40]Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 - [c39]Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS 2004: 463-473 - [c38]Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46 - 2003
- [j7]Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr:
Instruction Scheduler Generation for Retargetable Compilation. IEEE Des. Test Comput. 20(1): 34-41 (2003) - [c37]Rainer Leupers:
Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms. CC 2003: 290-302 - [c36]Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 - [c35]Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267 - [c34]Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973 - [c33]Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES 2003: 167-181 - [c32]Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers:
Improving Offset Assignment through Simultaneous Variable Coalescing. SCOPES 2003: 285-297 - 2002
- [b4]Andreas Hoffmann, Heinrich Meyr, Rainer Leupers:
Architecture exploration for embedded processors with LISA. Kluwer 2002, ISBN 978-1-4020-7338-0, pp. I-VIII, 1-230 - [j6]Rainer Leupers:
Compiler Design Issues for Embedded Processors. IEEE Des. Test Comput. 19(4): 51-58 (2002) - [c31]Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27 - [c30]Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr:
Application specific compiler/architecture codesign: a case study. LCTES-SCOPES 2002: 185-193 - 2001
- [b3]Rainer Leupers, Peter Marwedel:
Retargetable compiler technology for embedded systems - tools and applications. Kluwer 2001, ISBN 978-0-7923-7578-4, pp. I-XI, 1-175 - [j5]Jens Wagner, Rainer Leupers:
C compiler design for a network processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1302-1308 (2001) - [c29]Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel:
Optimized address assignment for DSPs with SIMD memory accesses. ASP-DAC 2001: 415-420 - [c28]Rainer Leupers, Daniel Kotte:
Variable partitioning for dual memory bank DSPs. ICASSP 2001: 1121-1124 - [c27]Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis:
Low-Energy DSP Code Generation Using a Genetic Algorithm. ICCD 2001: 431-437 - [c26]Jens Wagner, Rainer Leupers:
C Compiler Design for an Industrial Network Processor. LCTES/OM 2001: 155-164 - [c25]Jens Wagner, Rainer Leupers:
C Compiler Design for an Industrial Network Processor. OM@PLDI 2001: 155-164 - 2000
- [b2]Rainer Leupers:
Code optimization techniques for embedded processors - methods, algorithms, and tools. Kluwer 2000, ISBN 978-0-7923-7989-8, pp. I-VIII, 1-216 - [j4]Rainer Leupers, Steven Bashford:
Graph-based code selection techniques for embedded processors. ACM Trans. Design Autom. Electr. Syst. 5(4): 794-814 (2000) - [c24]Rainer Leupers:
Instruction Scheduling for Clustered VLIW DSPs. IEEE PACT 2000: 291-300 - [c23]Rainer Leupers:
Register allocation for common subexpressions in DSP data paths. ASP-DAC 2000: 235-240 - [c22]Rainer Leupers:
Code Selection for Media Processors with SIMD Instructions. DATE 2000: 4-8 - [c21]Rainer Leupers:
Code Generation for Embedded Processors. ISSS 2000: 173-179
1990 – 1999
- 1999
- [j3]Steven Bashford, Rainer Leupers:
Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Des. Autom. Embed. Syst. 4(2-3): 119-165 (1999) - [c20]Rainer Leupers, Johann Elste, Birger Landwehr:
Generation of Interpretive and Compiled Instruction Set Simulators. ASP-DAC 1999: 339-342 - [c19]Steven Bashford, Rainer Leupers:
Constraint Driven Code Selection for Fixed-Point DSPs. DAC 1999: 817-822 - [c18]Rainer Leupers:
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. DATE 1999: 105- - [c17]Rainer Leupers, Peter Marwedel:
Function inlining under code size constraints for embedded processors. ICCAD 1999: 253-256 - [c16]Anupam Basu, Rainer Leupers, Peter Marwedel:
Array Index Allocation under Register Constraints in DSP Programs. VLSI Design 1999: 330-335 - 1998
- [j2]Rainer Leupers, Peter Marwedel:
Retargetable Code Generation Based on Structural Processor Description. Des. Autom. Embed. Syst. 3(1): 75-108 (1998) - [c15]Rainer Leupers, Anupam Basu, Peter Marwedel:
Optimized Array Index Computation in DSP Programs. ASP-DAC 1998: 87-92 - [c14]Anupam Basu, Rainer Leupers, Peter Marwedel:
Register-Constrained Address Computation in DSP Programs. DATE 1998: 929-930 - [c13]Rainer Leupers, Fabian David:
A Uniform Optimization Technique for Offset Assignment Problems. ISSS 1998: 3-8 - [c12]Rainer Leupers:
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. ISSS 1998: 51- - 1997
- [b1]Rainer Leupers:
Retargetable code generation for digital signal processors. Kluwer 1997, ISBN 978-0-7923-9958-2, pp. I-X, 1-210 - [j1]Rainer Leupers, Peter Marwedel:
Time-constrained code compaction for DSPs. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 112-122 (1997) - [c11]Rainer Leupers, Peter Marwedel:
Retargetable generation of code selectors from HDL processor models. ED&TC 1997: 140-144 - 1996
- [c10]Rainer Leupers, Peter Marwedel:
Instruction selection for embedded DSPs with complex instructions. EURO-DAC 1996: 200-205 - [c9]Rainer Leupers, Peter Marwedel:
Algorithms for address assignment in DSP code generation. ICCAD 1996: 109-112 - [c8]Rainer Leupers, Peter Marwedel:
Instruction-Set Modeling for ASIP Code Generation. VLSI Design 1996: 77-80 - 1995
- [c7]Rainer Leupers, Peter Marwedel:
Using compilers for heterogeneous system design. PACT 1995: 273-276 - [c6]Rainer Leupers, Peter Marwedel:
A BDD-based frontend for retargetable compilers. ED&TC 1995: 239-243 - [c5]Rainer Leupers, Peter Marwedel:
Time-constrained code compaction for DSPs. ISSS 1995: 54-59 - 1994
- [c4]Peter Marwedel, Rainer Leupers:
Instruction set extraction from programmable structures. EURO-DAC 1994: 156-161 - [c3]Rainer Leupers, Wolfgang Schenk, Peter Marwedel:
Microcode Generation for Flexible Parallel Target Architectures. IFIP PACT 1994: 247-256 - [c2]Rainer Leupers, Wolfgang Schenk, Peter Marwedel:
Retargetable assembly code generation by bootstrapping. HLSS 1994: 88-93 - 1993
- [c1]Lorenz Ladage, Rainer Leupers:
Resistance Extraction using a Routing Algorithm. DAC 1993: 38-42
Coauthor Index
Gerd Ascheid
aka: Gerd H. Ascheid
aka: Gerd H. Ascheid
[c221] [j45] [c214] [j43] [c203] [c199] [i8] [j42] [j41] [c195] [c194] [c193] [c192] [c191] [c190] [c189] [c187] [i5] [c184] [c183] [c182] [c180] [c179] [c178] [c176] [c175] [c174] [c173] [j40] [c172] [c171] [c170] [c169] [c168] [c167] [c166] [c165] [j37] [j36] [j35] [j34] [j33] [c163] [c162] [c160] [c159] [c158] [c157] [c156] [c155] [c154] [j31] [c152] [c149] [c148] [c146] [c144] [c143] [c142] [c141] [c140] [c139] [c138] [c137] [c135] [j30] [j29] [c134] [c132] [c131] [c130] [c129] [c128] [c126] [c124] [c123] [c122] [c121] [c120] [c119] [j28] [j27] [j26] [c117] [c116] [c115] [c114] [c113] [c112] [c109] [c108] [c107] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [j25] [j24] [c97] [c95] [j21] [j20] [j19] [c92] [c90] [c89] [c88] [c87] [j18] [j17] [c85] [c84] [c82] [c81] [c79] [c78] [c77] [i2] [i1] [j14] [j13] [j12] [c76] [c75] [c74] [c73] [c72] [j11] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [j9] [c64] [c62] [c61] [c60] [c58] [c57] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [p1] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c36] [c33]
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
Robert Buecs
aka: Robert Lajos Bücs
aka: Robert Lajos Bücs
Juan Fernando Eusse
aka: Juan Fernando Eusse Giraldo
aka: Juan Fernando Eusse Giraldo
Gereon Führ
aka: Gereon Onnebrink
aka: Gereon Onnebrink
[j51] [i35] [j50] [c237] [c235] [c231] [i30] [i28] [j49] [j47] [c228] [c227] [c224] [c223] [c222] [c218] [i25] [i21] [i19] [j46] [c215] [c213] [c211] [c206] [c205] [c204] [i17] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [j44] [c202] [c201] [c197] [i9] [i7] [c193] [c192] [c188] [c187] [c186] [c185] [c181] [i4]
[c99] [j25] [j21] [j20] [j19] [c92] [c88] [c87] [j18] [j17] [c85] [c84] [c81] [c79] [c78] [c77] [i2] [i1] [j16] [j15] [j14] [j13] [j12] [c76] [c75] [c74] [c73] [b6] [j11] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [b5] [j9] [c64] [c62] [c61] [c60] [c58] [c57] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [j8] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j7] [c36] [c35] [c34] [c33] [b4] [c31] [c30]
Jan Weinstock
aka: Jan Henrik Weinstock
aka: Jan Henrik Weinstock
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