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ORCIDICSAMOS 2014: Samos, Greece
- XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014. IEEE 2014
- Tor M. Aamodt:
Scaling usable computing capability. i - Bruce L. Jacob:
High-bandwidth, high-capacity, low-power memory systems. ii - Paul Blinzer:
The Heterogeneous System Architecture: It's beyond the GPU. iii
Multiprocessors & Multicores
- Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios
, George Economakos:
Co-design of many-accelerator heterogeneous systems exploiting virtual platforms. 1-8 - Carlo Galuzzi, Alexander V. Veidenbaum:
Preface. 1 - Shreya Adyanthaya, Zhihui Zhang, Marc Geilen, Jeroen Voeten, Twan Basten, Ramon R. H. Schiffelers:
Robustness analysis of multiprocessor schedules. 9-17 - Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum:
Dynamic-vector execution on a general purpose EDGE chip multiprocessor. 18-25 - Giuseppe Massari, Edoardo Paone, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, William Fornaciari, Cristina Silvano:
Combining application adaptivity and system-wide Resource Management on multi-core platforms. 26-33 - Muneeb Khan, Erik Hagersten:
Resource conscious prefetching for irregular applications in multicores. 34-43
Dataflow
- Jörn W. Janneck, Simone Casale Brunet, Marco Mattavelli:
Characterizing communication behavior of dataflow programs using trace analysis. 44-50 - Stavros Tripakis, Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang:
On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations. 51-58 - Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. 59-66
Scheduling
- Timon Kelter, Hendrik Borghorst, Peter Marwedel:
WCET-aware scheduling optimizations for multi-core real-time systems. 67-74 - Ricardo S. Ferreira, Waldir Denver, Monica Magalhães Pereira, Jorge Quadros, Luigi Carro, Stephan Wong:
A run-time modulo scheduling by using a binary translation mechanism. 75-82
Memory Systems
- Goran Narancic, Patrick Judd, Di Wu, Islam Atta, Michel Elnacouzi, Jason Zebchuk, Jorge Albericio, Natalie D. Enright Jerger, Andreas Moshovos, Kyros Kutulakos, Serag Gadelrab:
Evaluating the memory system behavior of smartphone workloads. 83-92 - Zhenzhi Wu, Dake Liu:
Memory sharing techniques for multi-standard high-throughput FEC decoder. 93-98 - Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Speculative synchronization for coherence-free embedded NUMA architectures. 99-106
Performance Analysis & Evaluation
- Arthur Pyka, Mathias Rohde, Sascha Uhrig:
Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems. 107-114 - Sohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ahmed Elhossini, Ben H. H. Juurlink:
GPGPU workload characteristics and performance analysis. 115-124 - Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá Vayá, Christopher Bartels, Holger Blume:
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms. 125-132 - Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Pre-architectural performance estimation for ASIP design based on abstract processor models. 133-140
Architectures (Miscellanea)
- Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos:
Design space exploration for fair resource-allocated NoC architectures. 141-148 - Janne Helkala, Timo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg:
Variable length instruction compression on Transport Triggered Architectures. 149-155 - Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Hans Vandierendonck, Spyros Lalis:
Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs. 156-163 - Liana Dessandre Duenha, Marcelo Guedes, Henrique Almeida, Matheus Boy, Rodolfo Azevedo:
MPSoCBench: A toolset for MPSoC system level evaluation. 164-171
Power & Energy
- Karel De Vogeleer, Gérard Memmi, Pierre Jouvelot, Fabien Coelho:
Modeling the temperature bias of power consumption for nanometer-scale CPUs in application processors. 172-180 - Kim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz, Stefan Stattelmann, Björn Sander, Oliver Bringmann, Wolfgang Nebel, Wolfgang Rosenstiel:
An ESL timing & power estimation and simulation framework for heterogeneous socs. 181-190 - Anthony Gutierrez, Ronald G. Dreslinski, Trevor N. Mudge:
Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores. 191-198 - Philippe Clauss, Imen Fassi, Alexandra Jimborean:
Software-controlled processor stalls for time and energy efficient data locality optimization. 199-206
Reconfigurable Architectures
- Qingshan Tang, Habib Mehrez, Matthieu Tuna:
Multi-FPGA prototyping board issue: the FPGA I/O bottleneck. 207-214 - Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. 215-224 - Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan:
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. 225-232 - Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. 233-241
SystemC & Simultations
- Bastian Haetzer, Martin Radetzki:
Asynchronous parallel simulation with transaction events. 242-249 - Nicolas Ventroux, Julien Peeters, Tanguy Sassolas, James C. Hoe:
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations. 250-257 - Fabian Mischkalla, Wolfgang Müller:
Architectural low-power design using transaction-based system modeling and simulation. 258-265 - Fernando Akira Endo, Damien Couroussé, Henri-Pierre Charles:
Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5. 266-273
Algorithms & Modeling
- Dominik Reinhardt:
Ranking software components using a modified PageRank algorithm including safety aspects. 274-281 - Lazaros Papadopoulos, Ivan Walulya, Philippas Tsigas, Dimitrios Soudris, Brendan Barry:
Evaluation of message passing synchronization algorithms in embedded systems. 282-289 - Mark Westmijze, Marco Jan Gerrit Bekooij, Gerard J. M. Smit:
Efficient end-to-end latency distribution analysis for probabilistic time-triggered systems. 290-298 - Gregor Walla, Andreas Herkersdorf, Andre S. Enger, Andreas Barthels, Hans-Ulrich Michel:
An automotive specific MILP model targeting power-aware function partitioning. 299-306
Special Session on "Embedded Driver Assistance Systems - Initial Results of the DESERVE Artemis-JU-project"
- Matti Kutila, Pasi Pyykönen, Paul van Koningsbruggen, Nereo Pallaro, Joshué Pérez Rastelli:
The DESERVE project: Towards future ADAS functions. 308-313 - Florian Giesemann, Guillermo Payá Vayá, Holger Blume, Matthias Limmer, Werner Ritter:
A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications. 314-321 - Joshué Pérez, David González, Fawzi Nashashibi, Gwenaël Dunand, Fabio Tango, Nereo Pallaro, Andre Rolfsmeier:
Development and design of a platform for arbitration and sharing control applications. 322-328 - Clement Galko, Romain Rossi, Xavier Savatier:
Vehicle-Hardware-In-The-Loop system for ADAS prototyping and validation. 329-334 - Nico Mentzer, Guillermo Payá Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter:
Instruction-set extension for an ASIP-based SIFT feature extraction. 335-342 - Jens Klimke, Philipp Themann, Christoph Klas, Lutz Eckstein:
Definition of an embedded driver model for driving behavior prediction within the DESERVE platform. 343-350 - Frank Meinl, Martin Kunert, Holger Blume:
Massively parallel signal processing challenges within a driver assistant prototype framework first case study results with a novel MIMO-radar. 351-357
Special Session on "Brain-targeted and brain-inspired computing" 358 Introduction to the Special Session on "Brain-targeted and brain-inspired computing"
- Georgios Georgis, Dionysios I. Reisis, Panagiotis Skordilakis, Konstantinos S. Tsakalis, Ashfaque Bin Shafique, George Chatzikonstantis, George Lentaris:
Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms. 359-366 - Dimitrios Rodopoulos, Giorgos Chatzikonstantis, Andreas Pantelopoulos, Dimitrios Soudris, Chris I. De Zeeuw, Christos Strydis:
Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer. 367-374 - Babak Keshavarz Hedayati, Nikitas J. Dimopoulos, Arif Babul:
An analysis of dynamics of CA3b in Hippocampus. 375-383
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