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ORCID18th FDL 2015: Barcelona, Spain
- 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015. IEEE 2015, ISBN 978-1-4673-7735-5
Session 1: Clocks and Their Applications
- Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione:
Enabler-based synchronizer model for clock domain crossing static verification. 11-17 - Georg Gläser, Gregor Nitsche, Eckhard Hennig:
Temporal decoupling with error-bounded predictive quantum control. 18-23 - Hend Affes, Michel Auguin, François Verdier, Alain Pegatoquet:
A methodology for inserting clock-management strategies in transaction-level models of systemon- chips. 24-30
Special Session 1: Power Aware Modelling and Design
- Xiao Pan, Javier Moreno Molina, Christoph Grimm
:
Modeling power consumption at system-level for design of power integrity-aware AMS-circuits. 32-39 - Quentin Bramas, Wilfried Dron, Mariem Ben Fadhl, Khalil Hachicha, Patrick Garda, Sébastien Tixeuil:
WiSeBat: accurate energy benchmarking of wireless sensor networks. 40-47
Session 2: FMI and SystemC-AMS
- Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann:
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. 49-56 - Martin Krammer, Helmut Martin, Zoran Radmilovic, Simon Erker, Michael Karner:
Standard compliant co-simulation models for verification of automotive embedded systems. 57-64 - Sara Vinco, Michele Lora, Mark Zwolinski:
Conservative behavioural modelling in systemc-AMS. 65-72
Session 3: Design and Correctness
- Cristiano Bacelar de Oliveira, Ricardo Menotti, João M. P. Cardoso, Eduardo Marques:
A special-purpose language for implementing pipelined FPGA-based accelerators. 74-81 - Laurence Pierre:
Towards a toolchain for assertion-driven test sequence generation. 82-89 - Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Architectural system modeling for correct-by-construction RTL design. 90-97
Session 4: From MARTE Models to Initial Implementations
- Emad Samuel Malki Ebeid, Julio L. Medina, Davide Quaglia, Franco Fummi:
Extensions to the UML profile for MARTE for distributed embedded systems. 99-106 - David de la Fuente, Jesús Barba, Xerach Peña, Juan Carlos López, Pablo Peñil, Pablo Pedro Sanchez:
Building a dynamically reconfigurable system through a high development flow. 107-114
Special Session 2: High Integrity Multi-Core Modelling for Future Systems (Hi-MCM)
- Philipp Ittershagen, Kim Grüttner, Wolfgang Nebel:
Mixed-criticality system modelling with dynamic execution mode switching. 116-121 - Fernando Herrera, Pablo Peñil, Eugenio Villar:
Enhancing analysability and time predictability in UML/MARTE component-based application models. 122-129 - Asier Larrucea, Irune Agirre, Carlos Fernando Nicolás, Jon Pérez, Mikel Azkarate-askasua, Ton Trapman:
Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning. 130-137
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