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Uwe Deidersen
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2010 – 2019
- 2014
- [c6]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers. VLSI-SoC 2014: 1-6 - [c5]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm. VLSI-SoC (Selected Papers) 2014: 149-169 - 2013
- [c4]Uwe Deidersen, Dominik Auras, Gerd Ascheid:
A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection. ACM Great Lakes Symposium on VLSI 2013: 167-172 - 2012
- [c3]Carina Schmidt-Knorreck, Renaud Pacalet, Andreas Minwegen, Uwe Deidersen, Torsten Kempf, Raymond Knopp, Gerd Ascheid:
Flexible front-end processing for software defined radio applications using application specific instruction-set processors. DASIP 2012: 1-8 - [c2]Andreas Minwegen, Dominik Auras, Uwe Deidersen, Gerd Ascheid:
Architectures for MIMO-OFDM simplified decision directed channel estimation. ISCAS 2012: 2861-2864 - [c1]Dominik Auras, Andreas Minwegen, Uwe Deidersen:
Just-in-Time Verification in ADL-based processor design. ICSAMOS 2012: 1-6
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