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Bernardus Juurlink
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- affiliation: TU Berlin, Department of Computer Engineering and Microelectronics
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Books and Theses
- 2012
[b1]Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Chi Ching Chi, Arnaldo Azevedo, Cor Meenderinck, Alex Ramírez:
Scalable Parallel Programming Applied to H.264/AVC Decoding. Springer Briefs in Computer Science, Springer 2012, ISBN 978-1-4614-2229-7, pp. i-xiii, 1-101
Journal Articles
- 2022
- [j33]Sohan Lal
, Sharatchandra Varma Bogaraju, Ben H. H. Juurlink:
A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads. Int. J. Parallel Program. 50(2): 189-216 (2022) - 2021
- [j32]Biagio Cosenza, Nikita Popov, Ben H. H. Juurlink, Paul Richmond, Mozhgan Kabiri Chimeh, Carmine Spagnuolo, Gennaro Cordasco, Vittorio Scarano:
Easy and efficient agent-based simulations with the OpenABL language and compiler. Future Gener. Comput. Syst. 116: 61-75 (2021) - 2020
- [j31]Kaijie Fan, Biagio Cosenza, Ben H. H. Juurlink:
Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels. Comput. 8(2): 37 (2020) - [j30]Angela Pohl, Biagio Cosenza, Ben H. H. Juurlink:
Vectorization cost modeling for NEON, AVX and SVE. Perform. Evaluation 140-141: 102106 (2020) - 2018
- [j29]Hossein Amiri, Asadollah Shahbahrami, Angela Pohl, Ben H. H. Juurlink:
Performance evaluation of implicit and explicit SIMDization. Microprocess. Microsystems 63: 158-168 (2018) - [j28]Biao Wang, Diego F. de Souza, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink, Aleksandar Ilic, Nuno Roma, Leonel Sousa:
Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU. Signal Process. Image Commun. 62: 93-105 (2018) - 2017
- [j27]Philipp Habermann, Chi Ching Chi, Mauricio Alvarez-Mesa, Bernardus Juurlink:
Application-Specific Cache and Prefetching for HEVC CABAC Decoding. IEEE Multim. 24(1): 72-85 (2017) - [j26]Biao Wang, Diego F. de Souza, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink, Aleksandar Ilic, Nuno Roma, Leonel Sousa:
GPU Parallelization of HEVC In-Loop Filters. Int. J. Parallel Program. 45(6): 1515-1535 (2017) - 2015
- [j25]Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency. ACM Trans. Archit. Code Optim. 12(3): 32:1-32:26 (2015) - [j24]Biao Wang, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink:
Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL. IEEE Trans. Circuits Syst. Video Technol. 25(3): 525-531 (2015) - [j23]Chi Ching Chi, Mauricio Alvarez-Mesa, Benjamin Bross, Ben H. H. Juurlink, Thomas Schierl:
SIMD Acceleration for HEVC Decoding. IEEE Trans. Circuits Syst. Video Technol. 25(5): 841-855 (2015) - 2014
- [j22]Jan Hendrik Schönherr, Ben H. H. Juurlink, Jan Richling:
TACO: A scheduling scheme for parallel applications on multicore architectures. Sci. Program. 22(3): 223-237 (2014) - [j21]Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
Low-Power High-Efficiency Video Decoding using General-Purpose Processors. ACM Trans. Archit. Code Optim. 11(4): 56:1-56:25 (2014) - 2013
- [j20]Chi Ching Chi, Mauricio Alvarez-Mesa, Jan Lucas, Ben H. H. Juurlink, Thomas Schierl:
Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis. J. Signal Process. Syst. 71(3): 247-260 (2013) - 2012
- [j19]Ben H. H. Juurlink, Cor Meenderinck:
Amdahl's law for predicting the future of multicores considered harmful. SIGARCH Comput. Archit. News 40(2): 1-9 (2012) - [j18]Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink, Gordon Clare, Félix Henry, Stéphane Pateux, Thomas Schierl:
Parallel Scalability and Efficiency of HEVC Parallelization Approaches. IEEE Trans. Circuits Syst. Video Technol. 22(12): 1827-1838 (2012) - 2011
- [j17]Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero:
A Highly Scalable Parallel Implementation of H.264. Trans. High Perform. Embed. Archit. Compil. 4: 111-134 (2011) - 2010
- [j16]Arnaldo Azevedo, Ben H. H. Juurlink:
A Multidimensional Software Cache for Scratchpad-Based Systems. Int. J. Embed. Real Time Commun. Syst. 1(4): 1-20 (2010) - [j15]Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastián Isaza, Georgi Gaydadjiev:
The SARC Architecture. IEEE Micro 30(5): 16-29 (2010) - 2009
- [j14]Pepijn J. de Langen, Ben H. H. Juurlink:
Leakage-Aware Multiprocessor Scheduling. J. Signal Process. Syst. 57(1): 73-88 (2009) - [j13]Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis:
Instruction-Level Fault Tolerance Configurability. J. Signal Process. Syst. 57(1): 89-105 (2009) - [j12]Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez:
Parallel Scalability of Video Decoders. J. Signal Process. Syst. 57(2): 173-194 (2009) - 2008
- [j11]Ben H. H. Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis:
GRAAL: A Framework for Low-Power 3D Graphics Accelerators. IEEE Computer Graphics and Applications 28(4): 63-73 (2008) - [j10]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Versatility of extended subwords and the matrix register file. ACM Trans. Archit. Code Optim. 5(1): 5:1-5:30 (2008) - [j9]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors. IEEE Trans. Multim. 10(1): 43-51 (2008) - 2006
- [j8]Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis:
Avoiding Conversion and Rearrangement Overhead in SIMD Architectures. Int. J. Parallel Program. 34(3): 237-260 (2006) - 2005
- [j7]Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
The CSI multimedia architecture. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 1-13 (2005) - 2003
- [j6]Ben H. H. Juurlink, Petr Kolman, Friedhelm Meyer auf der Heide, Ingo Rieping:
Optimal broadcast on parallel locality models. J. Discrete Algorithms 1(2): 151-166 (2003) - [j5]Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Implementation of a streaming execution unit. J. Syst. Archit. 49(12-15): 599-617 (2003) - [j4]Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, Ingo Rieping:
The Paderborn University BSP (PUB) library. Parallel Comput. 29(2): 187-207 (2003) - 1998
- [j3]Ben H. H. Juurlink, Harry A. G. Wijshoff:
A Quantitative Comparison of Parallel Computation Models. ACM Trans. Comput. Syst. 16(3): 271-318 (1998) - [j2]Ben H. H. Juurlink, Jop F. Sibeyn, P. S. Rao:
Gossiping on Meshes and Tori. IEEE Trans. Parallel Distributed Syst. 9(6): 513-525 (1998) - 1996
- [j1]Ben H. H. Juurlink, Harry A. G. Wijshoff:
Communication Primitives for BSP Computers. Inf. Process. Lett. 58(6): 303-310 (1996)
Conference and Workshop Papers
- 2022
- [c133]Daniel Maier, Stefan Schirmeister, Ben H. H. Juurlink:
Effects of Approximate Computing on Workload Characteristics. ARCS 2022: 85-99 - [c132]Kaijie Fan, Biagio Cosenza, Ben H. H. Juurlink:
FLEXDP: flexible frequency scaling for energy-delay product optimization of GPU applications. CF 2022: 177-180 - [c131]Sohan Lal, Manuel Renz, Julian Hartmer, Ben H. H. Juurlink:
Memory Access Granularity Aware Lossless Compression for GPUs. IPDPS 2022: 1074-1084 - 2021
- [c130]Sohan Lal, Jan Lucas, Ben H. H. Juurlink:
QSLC: Quantization-Based, Low-Error Selective Approximation for GPUs. DATE 2021: 475-480 - [c129]Daniel Maier, Biagio Cosenza, Ben H. H. Juurlink:
ALONA: Automatic Loop Nest Approximation with Reconstruction and Space Pruning. Euro-Par 2021: 3-18 - [c128]Daniel Maier, Ben H. H. Juurlink:
Model-Based Loop Perforation. Euro-Par Workshops 2021: 549-554 - [c127]Gabriel L. Nazar, Pedro H. Kopper, Marcos T. Leipnitz, Ben H. H. Juurlink:
Lightweight Dual Modular Redundancy through Approximate Computing. SBESC 2021: 1-8 - 2020
- [c126]Mohammad Loni, Ali Zoljodi, Daniel Maier, Amin Majd, Masoud Daneshtalab, Mikael Sjödin, Ben H. H. Juurlink, Reza Akbari:
DenseDisp: Resource-Aware Disparity Map Estimation by Compressing Siamese Neural Architecture. CEC 2020: 1-8 - [c125]Yassin Kaddar, Angela Pohl, Ben H. H. Juurlink:
Accelerating The Vvc Decoder For Vector Length Agnostic Simd Architectures. ICME 2020: 1-6 - [c124]Philipp Habermann, Bernardus Juurlink, C. C. Chi, Mauricio Alvarez-Mesa:
Efficient Wavefront Parallel Processing for HEVC CABAC Decoding. PDP 2020: 339-343 - [c123]Sohan Lal, Ben H. H. Juurlink:
A Quantitative Study of Locality in GPU Caches. SAMOS 2020: 228-242 - 2019
- [c122]Jan Lucas, Ben H. H. Juurlink:
MEMPower: Data-Aware GPU Memory Power Model. ARCS 2019: 195-207 - [c121]Sohan Lal, Jan Lucas, Ben H. H. Juurlink:
SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs. DATE 2019: 1184-1189 - [c120]Kaijie Fan, Biagio Cosenza, Ben H. H. Juurlink:
Predictable GPUs Frequency Scaling for Energy and Performance. ICPP 2019: 52:1-52:10 - [c119]Angela Pohl, Mirko Greese, Biagio Cosenza, Ben H. H. Juurlink:
A Performance Analysis of Vector Length Agnostic Code. HPCS 2019: 159-164 - [c118]Nadjib Mammeri, Markus Neu, Sohan Lal, Ben H. H. Juurlink:
Performance Counters based Power Modeling of Mobile GPUs using Deep Learning. HPCS 2019: 193-200 - [c117]Matthias Goebel, Kai Norman Clasen, Robert Drehmel, Ben H. H. Juurlink:
Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC. HPCS 2019: 209-216 - [c116]Daniel Maier, Nadjib Mammeri, Biagio Cosenza, Ben H. H. Juurlink:
Approximating Memory-bound Applications on Mobile GPUs. HPCS 2019: 329-335 - [c115]Apurv Ashish, Sohan Lal, Ben H. H. Juurlink:
An Efficient Lightweight Framework for Porting Vision Algorithms on Embedded SoCs. IESS 2019: 130-141 - [c114]Philipp Habermann, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
A Bin-Based Bitstream Partitioning Approach for Parallel CABAC Decoding in Next Generation Video Coding. IPDPS 2019: 1053-1062 - [c113]Angela Pohl, Biagio Cosenza, Ben H. H. Juurlink:
Portable Cost Modeling for Auto-Vectorizers. MASCOTS 2019: 359-369 - [c112]Nadjib Mammeri, Ben H. H. Juurlink:
VComputeLib: Enabling Cross-Platform GPGPU on Mobile and Embedded GPUs. MoMM 2019: 242-251 - 2018
- [c111]Daniel Maier, Biagio Cosenza, Ben H. H. Juurlink:
Local memory-aware kernel perforation. CGO 2018: 278-287 - [c110]Angela Pohl, Biagio Cosenza, Ben H. H. Juurlink:
Cost Modelling for Vectorization on ARM. CLUSTER 2018: 644-645 - [c109]Jan Lucas, Sohan Lal, Ben H. H. Juurlink:
Optimal DC/AC data bus inversion coding. DATE 2018: 1063-1068 - [c108]Biagio Cosenza, Nikita Popov, Ben H. H. Juurlink, Paul Richmond, Mozhgan Kabiri Chimeh, Carmine Spagnuolo, Gennaro Cordasco, Vittorio Scarano:
OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations. Euro-Par 2018: 505-518 - [c107]Nadjib Mammeri, Ben H. H. Juurlink:
VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs. IISWC 2018: 25-35 - [c106]Matthias Goebel, Ilja Behnke, Ahmed Elhossini, Ben H. H. Juurlink:
An Application-Specific Memory Management Unit for FPGA-SoCs. IPDPS Workshops 2018: 222-225 - [c105]Christina Quast, Angela Pohl, Biagio Cosenza, Ben H. H. Juurlink, Rainer Schwemmer:
Accelerating the RICH Particle Detector Algorithm on Intel Xeon Phi. PDP 2018: 368-375 - [c104]Angela Pohl, Biagio Cosenza, Ben H. H. Juurlink:
Control Flow Vectorization for ARM NEON. SCOPES 2018: 66-75 - 2017
- [c103]Matthias Göbel, Ahmed Elhossini, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. ARC 2017: 241-252 - [c102]Nikita Popov, Biagio Cosenza, Ben H. H. Juurlink, Dmitry Stogov:
Static optimization in PHP 7. CC 2017: 65-75 - [c101]Ben H. H. Juurlink, Jan Lucas, Nadjib Mammeri, Georgios Keramidas, Katerina Pontzolkova, Ignacio Aransay, Chrysa Kokkala, Martyn Bliss, Andrew Richards:
Enabling GPU software developers to optimize their applications - The LPGPU2 approach. DASIP 2017: 1-6 - [c100]Matthias Göbel, Ahmed Elhossini, Ben H. H. Juurlink:
A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign. DSD 2017: 533-537 - [c99]Philipp Habermann, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
Syntax Element Partitioning for high-throughput HEVC CABAC decoding. ICASSP 2017: 1308-1312 - [c98]Biagio Cosenza, Juan José Durillo, Stefano Ermon, Ben H. H. Juurlink:
Autotuning Stencil Computations with Structural Ordinal Regression Learning. IPDPS 2017: 287-296 - [c97]Sohan Lal, Jan Lucas, Ben H. H. Juurlink:
E^2MC: Entropy Encoding Based Memory Compression for GPUs. IPDPS 2017: 1119-1128 - [c96]Biagio Cosenza, Juan José Durillo, Stefano Ermon, Ben H. H. Juurlink:
Stencil Autotuning with Ordinal Regression: Extended Abstract. SCOPES 2017: 72-75 - [c95]Ben H. H. Juurlink, Jan Lucas, Nadjib Mammeri, Martyn Bliss, Georgios Keramidas, Chrysa Kokkala, Andrew Richards:
The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract. SCOPES 2017: 76-80 - 2016
- [c94]Maurice Peemen, Runbin Shi, Sohan Lal, Ben H. H. Juurlink, Bart Mesman, Henk Corporaal:
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision. DATE 2016: 1604-1609 - [c93]Lester Kalms, Ahmed Elhossini, Ben H. H. Juurlink:
FPGA based hardware accelerator for KAZE feature extraction algorithm. FPT 2016: 281-284 - [c92]Jan Lucas, Ben H. H. Juurlink:
ALUPower: Data Dependent Power Consumption in GPUs. MASCOTS 2016: 95-104 - [c91]Biao Wang, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink, Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa:
Efficient HEVC decoder for heterogeneous CPU with GPU systems. MMSP 2016: 1-6 - [c90]Angela Pohl, Biagio Cosenza, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink:
An evaluation of current SIMD programming models for C++. WPMVP@PPoPP 2016: 3:1-3:8 - 2015
- [c89]Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink:
An Efficient and Flexible FPGA Implementation of a Face Detection System. ARC 2015: 243-254 - [c88]Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers:
Multi/many-core programming: where are we standing? DATE 2015: 1708-1717 - [c87]Matthias Göbel, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis. FCCM 2015: 32 - [c86]Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink:
An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only). FPGA 2015: 261 - [c85]Tamer Dallou, Nina Engelhardt, Ahmed Elhossini, Ben H. H. Juurlink:
Nexus#: A Distributed Hardware Task Manager for Task-Based Programming Models. IPDPS 2015: 1129-1138 - [c84]Philipp Habermann, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
Optimizing HEVC CABAC Decoding with a Context Model Cache and Application-Specific Prefetching. ISM 2015: 429-434 - [c83]Michael Andersch, Jan Lucas, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
On latency in GPU throughput microarchitectures. ISPASS 2015: 169-170 - [c82]Gabriel Cebrián-Márquez, Chi Ching Chi, José Luis Martínez, Pedro Cuenca, Mauricio Alvarez-Mesa, Sergio Sanz Rodríguez, Ben H. H. Juurlink:
Reducing HEVC encoding complexity using two-stage motion estimation. VCIP 2015: 1-4 - 2014
- [c81]Gervin Thomas, Ahmed Elhossini, Ben H. H. Juurlink:
A generic implementation of a quantified predictor on FPGAs. ACM Great Lakes Symposium on VLSI 2014: 255-260 - [c80]Nina Engelhardt, Tamer Dallou, Ahmed Elhossini, Ben H. H. Juurlink:
An Integrated Hardware-Software Approach to Task Graph Management. HPCC/CSS/ICESS 2014: 392-399 - [c79]Sohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ahmed Elhossini, Ben H. H. Juurlink:
GPGPU workload characteristics and performance analysis. ICSAMOS 2014: 115-124 - 2013
- [c78]Benjamin Bross, Valeri George, Mauricio Alvarez-Mesa, Tobias Mayer, Chi Ching Chi, Jens Brandenburg, Thomas Schierl, Detlev Marpe, Ben H. H. Juurlink:
HEVC performance and complexity for 4K video. ICCE-Berlin 2013: 44-47 - [c77]Jan Lucas, Sohan Lal, Michael Andersch, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator. ISPASS 2013: 97-106 - 2012
- [c76]Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben H. H. Juurlink, Kees Goossens:
A Predictor-Based Power-Saving Policy for DRAM Memories. DSD 2012: 882-889 - [c75]Biao Wang, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink:
An Optimized Parallel IDCT on Graphics Processing Units. Euro-Par Workshops 2012: 155-164 - [c74]Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink, Valeri George, Thomas Schierl:
Parallel video decoding in the emerging HEVC standard. ICASSP 2012: 1545-1548 - [c73]Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink, Valeri George, Thomas Schierl:
Improving the parallelization efficiency of HEVC decoding. ICIP 2012: 213-216 - [c72]Tamer Dallou, Ben H. H. Juurlink:
Hardware-Based Task Dependency Resolution for the StarSs Programming Model. ICPP Workshops 2012: 367-374 - [c71]Stefan Hauser, Nico Moser, Ben H. H. Juurlink:
SynZEN: A hybrid TTA/VLIW architecture with a distributed register file. NORCHIP 2012: 1-4 - [c70]Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink:
Programming parallel embedded and consumer applications in OpenMP superscalar. PPoPP 2012: 281-282 - [c69]Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink:
Using OpenMP superscalar for parallelization of embedded and consumer applications. ICSAMOS 2012: 23-32 - 2011
- [c68]Arnaldo Azevedo, Ben H. H. Juurlink:
An Instruction to Accelerate Software Caches. ARCS 2011: 158-170 - [c67]Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink:
Composable local memory organisation for streaming applications on embedded MPSoCs. Conf. Computing Frontiers 2011: 23 - [c66]Cor Meenderinck, Ben H. H. Juurlink:
Nexus: Hardware Support for Task-Based Programming. DSD 2011: 442-445 - [c65]Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström:
Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP 2011: 622-631 - [c64]Chi Ching Chi, Ben H. H. Juurlink:
A QHD-capable parallel H.264 decoder. ICS 2011: 317-326 - [c63]Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström:
Poster: implications of merging phases on scalability of multi-core architectures. ICS 2011: 380 - [c62]Ben H. H. Juurlink:
Multi-Core - the Future of Embedded Systems. MBMV 2011: 111-111 - 2010
- [c61]Demid Borodin, Ben H. H. Juurlink:
Protective redundancy overhead reduction using instruction vulnerability factor. Conf. Computing Frontiers 2010: 319-326 - [c60]Demid Borodin, Ben H. H. Juurlink:
Instruction precomputation with memoization for fault detection. DATE 2010: 1665-1668 - [c59]Cor Meenderinck, Ben H. H. Juurlink:
A Case for Hardware Task Management Support for the StarSS Programming Model. DSD 2010: 347-354 - [c58]Martijn Briejer, Cor Meenderinck, Ben H. H. Juurlink:
Extending the Cell SPE with Energy Efficient Branch Prediction. Euro-Par (1) 2010: 304-315 - [c57]Chi Ching Chi, Ben H. H. Juurlink, Cor Meenderinck:
Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine. ICS 2010: 105-114 - 2009
- [c56]Asadollah Shahbahrami, Ben H. H. Juurlink:
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. APPT 2009: 389-407 - [c55]Cor Meenderinck, Ben H. H. Juurlink:
Specialization of the Cell SPE for Media Applications. ASAP 2009: 46-52 - [c54]Arnaldo P. Azevedo Filho, Ben H. H. Juurlink:
Scalar Processing Overhead on SIMD-Only Architectures. ASAP 2009: 183-190 - [c53]Pepijn J. de Langen, Ben H. H. Juurlink:
Limiting the number of dirty cache lines. DATE 2009: 670-675 - [c52]Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxiras:
Instruction Precomputation for Fault Detection. DSD 2009: 91-99 - [c51]Asadollah Shahbahrami, Ben H. H. Juurlink:
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. DSD 2009: 497-504 - [c50]Gerard J. M. Smit, Gerrit F. van der Hoeven, Jan Friso Groote, Ralph H. J. M. Otten, Hans Tonino, Ben H. H. Juurlink, Boudewijn R. H. M. Haverkort:
The 3TU embedded systems master in the Netherlands. WESE@ESWEEK 2009: 8-12 - [c49]Pedro C. Diniz, Ben H. H. Juurlink, Alain Darte, Wolfgang Karl:
Introduction. Euro-Par 2009: 295-296 - [c48]Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez:
Parallel H.264 Decoding on an Embedded Multicore Processor. HiPEAC 2009: 404-418 - [c47]Cor Meenderinck, Ben H. H. Juurlink:
Intra-vector SIMD instructions for core specialization. ICCD 2009: 479-484 - [c46]Mauricio Alvarez-Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero:
Scalability of Macroblock-level Parallelism for H.264 Decoding. ICPADS 2009: 236-243 - [c45]Arnaldo Azevedo, Ben H. H. Juurlink:
An efficient software cache for H.264 motion compensation. SoC 2009: 147-150 - 2008
- [c44]Pepijn J. de Langen, Ben H. H. Juurlink:
Memory copies in multi-level memory systems. ASAP 2008: 281-286 - [c43]Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink:
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. DSD 2008: 189-194 - [c42]Demid Borodin, Ben H. H. Juurlink:
A Low-Cost Cache Coherence Verification Method for Snooping Systems. DSD 2008: 219-227 - [c41]Cor Meenderinck, Ben H. H. Juurlink:
(When) Will CMPs Hit the Power Wall?. Euro-Par Workshops 2008: 184-193 - [c40]Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez:
Analysis of video filtering on the cell processor. ISCAS 2008: 488-491 - [c39]Asadollah Shahbahrami, Ben H. H. Juurlink:
Optimization of Content-Based Image Retrieval Functions. ISM 2008: 607-612 - 2007
- [c38]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
SIMD Vectorization of Histogram Functions. ASAP 2007: 174-179 - [c37]Jie Tao, Asadollah Shahbahrami, Ben H. H. Juurlink, Rainer Buchty, Wolfgang Karl, Stamatis Vassiliadis:
Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool. ISM 2007: 153-160 - [c36]Pepijn J. de Langen, Ben H. H. Juurlink:
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors. SAMOS 2007: 75-85 - [c35]Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis:
Instruction-Level Fault Tolerance Configurability. ICSAMOS 2007: 110-117 - 2006
- [c34]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. CASES 2006: 293-303 - [c33]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Improving the memory behavior of vertical filtering in the discrete wavelet transform. Conf. Computing Frontiers 2006: 253-260 - [c32]Pepijn J. de Langen, Ben H. H. Juurlink:
Leakage-aware multiprocessor scheduling for low power. IPDPS 2006 - [c31]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File. ISM 2006: 37-46 - 2005
- [c30]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform. ASAP 2005: 393-398 - [c29]Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Matrix register file and extended subwords: two techniques for embedded media processors. Conf. Computing Frontiers 2005: 171-179 - [c28]Stephan Suijkerbuijk, Ben H. H. Juurlink:
Implementing Hardware Multithreading in a VLIW Architecture. IASTED PDCS 2005: 674-679 - [c27]Ben H. H. Juurlink, Asadollah Shahbahrami, Stamatis Vassiliadis:
Avoiding data conversions in embedded media processors. SAC 2005: 901-902 - 2004
- [c26]Ben H. H. Juurlink, Pepijn J. de Langen:
Dynamic techniques to reduce memory traffic in embedded systems. Conf. Computing Frontiers 2004: 192-201 - [c25]Pepijn J. de Langen, Ben H. H. Juurlink:
Reducing traffic generated by conflict misses in caches. Conf. Computing Frontiers 2004: 235-239 - [c24]Ben H. H. Juurlink:
Approximating the optimal replacement algorithm. Conf. Computing Frontiers 2004: 313-319 - [c23]Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen:
Accelerating the secure remote password protocol using reconfigurable hardware. Conf. Computing Frontiers 2004: 471-480 - [c22]Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
Scene Management Models and Overlap Tests for Tile-Based Rendering. DSD 2004: 424-431 - [c21]Pyrrhos Stathis, Dmitry Cheresiz, Stamatis Vassiliadis, Ben H. H. Juurlink:
Sparse Matrix Transpose Unit. IPDPS 2004 - [c20]Iosif Antochi, Bernardus Juurlink, Stamatis Vassiliadis, Petri Liuha:
Efficient tile-aware bounding-box overlap test for tile-based rendering. SoC 2004: 165-168 - [c19]Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
GraalBench: a 3D graphics benchmark suite for mobile phones. LCTES 2004: 1-9 - [c18]Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
Memory Bandwidth Requirements of Tile-Based Rendering. SAMOS 2004: 323-332 - 2003
- [c17]Ben H. H. Juurlink:
Unified Dual Data Caches. DSD 2003: 33-40 - 2002
- [c16]Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Implementation of a Streaming Execution Unit. DSD 2002: 156-165 - [c15]Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Performance Scalability of Multimedia Instruction Set Extensions. Euro-Par 2002: 849-860 - [c14]Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Architectural Support for 3D Graphics in the Complex Streamed Instruction Set. IASTED PDCS 2002: 531-536 - 2001
- [c13]Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff:
Implementation and Evaluation of the Complex Streamed Instruction Set. IEEE PACT 2001: 73-82 - [c12]Dmitri Tcheressiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Performance of the Complex Streamed Instruction Set on Image Processing Kernels. Euro-Par 2001: 678-686 - 2000
- [c11]Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis:
Counter Based Superscalar Instruction Issuing. EUROMICRO 2000: 1307-1315 - [c10]Stamatis Vassiliadis, Ben H. H. Juurlink, Edwin A. Hakkennes:
Complex Streamed Instructions: Introduction and Initial Evaluatio. EUROMICRO 2000: 1400- - [c9]Ben H. H. Juurlink, Petr Kolman, Friedhelm Meyer auf der Heide, Ingo Rieping:
Optimal broadcast on parallel locality models. SIROCCO 2000: 221-225 - 1999
- [c8]Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, Ingo Rieping:
The Paderborn University BSP (PUB) Library - Design, Implementation and Performance. IPPS/SPDP 1999: 99-104 - 1998
- [c7]Ben H. H. Juurlink:
Experimental Validation of Parallel Computation Models on the Intel Paragon. IPPS/SPDP 1998: 492-497 - [c6]Micah Adler, Wolfgang Dittrich, Ben H. H. Juurlink, Miroslaw Kutylowski, Ingo Rieping:
Communication-Optimal Parallel Minimum Spanning Tree Algorithms (Extended Abstract). SPAA 1998: 27-36 - 1996
- [c5]Ben H. H. Juurlink, Harry A. G. Wijshoff:
The E-BSP Model: Incorporating General Locality and Unbalanced Communication into the BSP Model. Euro-Par, Vol. II 1996: 339-347 - [c4]Ben H. H. Juurlink, P. S. Rao, Jop F. Sibeyn:
Worm-Hole Gossiping on Meshes. Euro-Par, Vol. I 1996: 361-369 - [c3]Harry A. G. Wijshoff, Ben H. H. Juurlink:
A Quantitative Comparison of Parallel Computation Models. SPAA 1996: 13-24 - 1994
- [c2]Ben H. H. Juurlink, Harry A. G. Wijshoff:
The Parallel Hierarchical Memory Model. SWAT 1994: 240-251 - 1993
- [c1]Ben H. H. Juurlink, Harry A. G. Wijshoff:
Experiences with a Model for Parallel Computation. PODC 1993: 87-96
Coauthor Index
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