default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDASP-DAC 1998: Yokohama, Japan
- Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998. IEEE 1998, ISBN 0-7803-4425-1
Session 1A: High-Speed Design Techniques
- Kimikazu Sano, Koichi Narahara, Koichi Murata, Taiichi Otsuji, Kiyomitsu Onodera:
High-speed GaAs MESFET Digital IC Design for Optical Communication Systems. 1-5 - Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani:
Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications. 7-12 - Simon Cimin Li, Reggie Chien, Jerry Chien, Kaung-Long Lin:
A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower. 13-18
Session 1B: Hardware/Software Codesign I
- Sri Parameswaran:
HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). 19-22 - Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators. 23-33
Session 1C: Technology CAD for Interconnections and Environments
- Hiroshi Kawaguchi
, Takayasu Sakurai:
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. 35-43 - Davide Pandini, Primo Scandolara, Carlo Guardiani:
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. 45-50 - Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi:
A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs. 51-56
Session 1D: (Design General Manager Panel) Design Technology Challenges in the Design Productivity Crisis
Session 2A: Combinational Logic Synthesis
- Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
New Methods to Find Optimal Non-Disjoint Bi-Decompositions. 59-68 - Debatosh Debnath, Tsutomu Sasao:
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. 69-74 - Gueesang Lee, Rolf Drechsler:
ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. 75-80 - Christoph Meinel, Fabio Somenzi, Thorsten Theobald:
Function Decomposition and Synthesis Using Linear Sifting. 81-86
Session 2B: Compiler for Embedded Processors
- Rainer Leupers, Anupam Basu, Peter Marwedel:
Optimized Array Index Computation in DSP Programs. 87-92 - Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe:
Binding and Scheduling Algorithms for Highly Retargetable Compilation. 93-98 - Hui Guo, Sri Parameswaran:
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. 99-104 - Chunho Lee, Miodrag Potkonjak:
Quantitative Selection of Media Benchmarks. ASP-DAC 1998: 105-110
Session 2C: Technology CAD for Lowest Level Design
- Morikazu Tsuno, Masato Suga, Masayasu Tanaka, Kentaro Shibahara, Mitiko Miura-Mattausch, Masataka Hirose:
Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET's. 111-116 - Seiichiro Yamaguchi, Hiroshi Goto:
Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be Made. ASP-DAC 1998: 117-121 - Ute Feldmann, Ronald Kakoschke, Mitiko Miura-Mattausch, G. Schraud:
Concurrent Technology, Device, and Circuit Development for EEPROMs. 123-128 - Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori:
TCAD/DA for MPU and ASIC Development. ASP-DAC 1998: 129-134
Session 2D (Panel & Embedded Tutorial): Coupling of Synthesis and Layout: Challenges and Solutions
- Massoud Pedram:
Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial). 137-142
Session 3A: DSP System Design
- Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku:
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. 145-150 - Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar:
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. 151-156 - Sung Hyun Yoon, Myung Hoon Sunwoo:
An Efficient Variable-Length Tap FIR Filter Chip. 157-161
Session 3B: System Simulation
- Kaoru Suzuki, Shunsuke Miyamoto, Masato Kurosaki, Junji Nakagoshi:
Effective Simulation for the Giga-scale Massively Parallel Supercomputer SR2201. 163-168 - Mitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki:
A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture. 169-175 - Wonyong Sung, Soonhoi Ha:
A Hardware Software Cosimulation Backplane with Automatic Interface Generation. 177-182
Session 3C: Asynchronous Logic Synthesis
- Mohit Sahni, Takashi Nanya:
On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. 183-189 - Uisok Kim, Dong-Ik Lee:
Practical Synthesis of Speed-Independent Circuits Using Unfoldings. 191-196 - Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura:
Automated Design of Wave Pipelined Multiport Register Files. 197-202
Session 3D: (Invited Talks) Design and EDA Road Map
Session 4A: Design for Testability
- Sujit Dey, Anand Raghunathan, Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial). 205-210 - Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara:
Partial Scan Design Methods Based on Internally Balanced Structure. 211-216
Session 4B: Model Checking: Its Basics and Reality
- Masahiro Fujita:
Model Checking: Its Basics and Reality (Embedded Tutorial). 217-222
Session 4C: Pass Transister Logic
- Kazuo Taki:
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial). 223-226 - Yasuhiko Sasaki, Kunihito Rikino, Kazuo Yano:
ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis. 227-232
Session 4D (Panel Discussion): Upcoming Deep Sub Micron EDA Tool Problem
Session 5A: Towards New EDA Standards
- Dinesh R. Bettadapur:
Software Licensing Models in the EDA Industry. 235-239 - Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi:
Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. 241-248 - Donald Cottrell, David Mallis, Joseph Morrell:
CHDStd - A Model for Deep Submicron Design Tools. 249-255 - S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams:
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis. 257-260 - Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki:
ATM Cell Modelling using Objective VHDL. 261-264
Session 5B: High-Level and System-Level Synthesis
- Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. 265-274 - Hiroyuki Tomiyama, Hiroto Yasuura:
Module Selection Using Manufacturing Information. 275-281 - Inki Hong, Miodrag Potkonjak:
Techniques for Functional Test Pattern Execution. 283-288 - Inki Hong, Miodrag Potkonjak, Ramesh Karri:
Heterogeneous BISR-approach using System Level Synthesis Flexibility. 289-294
Session 5C: Performance Driven Layout
- Jinan Lou, Amir H. Salek, Massoud Pedram:
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits. 295-300 - Susumu Kobayashi, Masato Edahiro, Mikio Kubo:
Scan-chain Optimization Algorithms for Multiple Scan-paths. ASP-DAC 1998: 301-306 - Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design. 307-312 - Jaewon Oh, Massoud Pedram:
Power Reduction in Microprocessor Chips by Gated Clock Routing. 313-318
Session 5D (Special Session): University LSI Design Contest
- Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor. 319-320 - Tohru Ishihara, Hiroto Yasuura:
Power-Pro: Programmable Power Management Architecture. 321-322 - Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. 323-324 - Jin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Nam, Chang-Ho Ryu, Jang-Ho Cho, Chong-Min Kyung:
Metacore: A Configurable and Instruction Level Extensible DSP Core. 325-326 - Ho Keun Jang:
A Design of Sound Synthesis IC. 327-328 - Se Young Eun, Myung Hoon Sunwoo:
An Effcient 2-D Convolver Chip for Real Time Image Processing. 329-330 - Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda:
FPGA for High-Performance Bit-Serial Pipeline Datapath. 331-332 - Keiichi Hirano, Taizou Ono, Hiroyuki Kurino, Mitsumasa Koyanagi:
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. 333-334 - Mark A. Bickerstaff, T. Arivoli, Philip J. Ryan, Neil Weste, David J. Skellern:
A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter. 335-336 - Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. 337-338 - Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa:
A CMOS Smart Image Sensor LSI for Focal-Plane Compression. 339-340 - Changsik Yoo, Wonchan Kim:
A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. 341-342 - Takayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hatori:
Motion Adaptive Image Sensor. 343-344
Session 6A: Digital PLL & Timing Design
- Anirudh Devgan, Sandip Kundu:
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). 345 - Tae Hun Kim, Beomsup Kim:
Dual-loop Digital PLL Design for Adaptive Clock Recovery. 347-352
Session 6B: Hardware/Software Codesign II
- Jörg Henkel, Rolf Ernst:
High-Level Estimation Techniques for Usage in Hardware/Software Co-Design. 353-360 - Jinhwan Jeon, Kiyoung Choi:
Loop Pipelining in Hardware-Software Partitioning. 361-366 - Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi:
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. 367-372
Session 6C: Layout Optimization and Verification
- Jiang-An He, Hideaki Kobayashi:
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization. 373-378 - Wonjong Kim, Hyunchul Shin:
Hierarchical LVS Based on Hierarchy Rebuilding. 379-384 - Toshiyuki Hama, Hiroaki Etoh:
Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening. 385-390
Session 6D (Invited Talk & Embedded Tutorial): Interconnections and Packaging for High Speed and High Frequency PCB/MCM
- Tim A. Schreyer:
Tool Capabilities Needed for Designing 100 MHz Interconnects. 391-395 - Yuji Tarui, Takehiro Takahashi, Noboru Schibuya:
Development of a Support Tool for PCB Design with EMC Constraint. 397-402 - Tetsuhisa Mido, Kunihiro Asada:
An Analysis on VLSI Interconnection Considering Skin Effect. ASP-DAC 1998: 403-408
Session 7A: High-Performance CMOS Circuits
- X. Zeng, P. S. Tang, C. K. Tse:
Design of Nonlinear Switched-Current Circuits Using Building Block Approach. ASP-DAC 1998: 409-414 - Tae-Min Kim, Gun Sun Shin:
A Circuit Design of 16x16 Multiplier Using Redundant Binary Arithmetic. ASP-DAC 1998: 415 - Massoud Pedram, Qing Wu, Xunwei Wu:
A New Design for Double Edge Triggered Flip-flops. ASP-DAC 1998: 417-421
Session 7B: Decision Diagrams
- Bwolen Yang, Yirng-An Chen, Randal E. Bryant, David R. O'Hallaron:
Space- and Time-Efficient BDD Construction via Working Set Control. 423-432 - Rolf Drechsler, Stefan Höreth:
Manipulation of *BMDs. 433-438 - Radomir S. Stankovic, Tsutomu Sasao:
Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. 439-446
Session 7C: Reconfigurable Systems
- Toshiaki Miyazaki:
Reconfigurable Systems: A Survey (Embedded Tutorial). 447-452 - Hideharu Amano, Yuichiro Shibata:
Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). 453-457
Session 7D (Panel Discussion): Asian-Pacific LSI Business in the 21st Century
Session 8A: Testing
- Miyako Tandai, Takao Shinsha:
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction. 463-468 - Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya:
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. 469-474 - Reza Sedaghat-Maman, Erich Barke:
Real Time Fault Injection Using Logic Emulators. 475-479 - João P. Marques Silva:
Integer Programming Models for Optimization Problems in Test Generation. 481-487
Session 8B: Analog CAD
- Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo:
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling. 489-494 - Markus Wolf, Ulrich Kleine, Frédéric Schafer:
A Novel Design Assistant for Analog Circuits. 495-500 - Chuanjin Richard Shi, Michael W. Tian:
Automatic Test Generation for Linear Analog Circuits under Parameter Variations. ASP-DAC 1998: 501-506 - Reiji Suda, Yoshio Oyanagi:
The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis. 507-512
Session 8C: Physical Design for FPGA
- Rongzheng Zhou, Jiarong Tong, Pushan Tang:
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. ASP-DAC 1998: 513-518 - Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. 519-526 - Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki, Akihiro Tsutsui:
An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing Resources. 527-533 - Jiaofeng Pan, Yu-Liang Wu, C. K. Wong:
On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. 535-540
Session 8D (Panel & Embedded Tutorial): The Next-Generation System Level Design Language
Session 9A: Analog HDL
- C.-J. Richard Shi:
Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial). 543
Session 9B: System-Level Power Minimization
- Sri Parameswaran, Hui Guo:
Power Reduction in Pipelines. 545-550 - Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho:
A Hybrid Power Model for RTL Power Estimation. 551-556 - Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith:
Synthesis of Power Efficient Systems-on-Silicon. 557-562
Session 9C: Floorplannning
- Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani:
Air-Pressure-Model-Based Fast Algorithms for General Floorplan. 563-570 - Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani:
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. 571-576 - Tetsushi Koide, Shin'ichi Wakabayashi:
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. 577-583
Session 9D (Invited Talks): LSI Designs in Multimedia Era
- Neil Weste, David J. Skellern, Terry Percival:
VLSI for Multimedia U-NII WLANs. 585-587 - Takao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Isao Shirakawa:
Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. 589-594 - Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa:
CMOS Image Sensors with Video Compression. 595-600
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-10 21:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
