ASP-DAC 1998: Yokohama, Japan

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Session 1A: High-Speed Design Techniques

Session 1B: Hardware/Software Codesign I

Session 1C: Technology CAD for Interconnections and Environments

Session 1D: (Design General Manager Panel) Design Technology Challenges in the Design Productivity Crisis

Session 2A: Combinational Logic Synthesis

Session 2B: Compiler for Embedded Processors

Session 2C: Technology CAD for Lowest Level Design

Session 2D (Panel & Embedded Tutorial): Coupling of Synthesis and Layout: Challenges and Solutions

Session 3A: DSP System Design

Session 3B: System Simulation

Session 3C: Asynchronous Logic Synthesis

Session 3D: (Invited Talks) Design and EDA Road Map

Session 4A: Design for Testability

Session 4B: Model Checking: Its Basics and Reality

Session 4C: Pass Transister Logic

Session 4D (Panel Discussion): Upcoming Deep Sub Micron EDA Tool Problem

Session 5A: Towards New EDA Standards

Session 5B: High-Level and System-Level Synthesis

Session 5C: Performance Driven Layout

Session 5D (Special Session): University LSI Design Contest

Session 6A: Digital PLL & Timing Design

Session 6B: Hardware/Software Codesign II

Session 6C: Layout Optimization and Verification

Session 6D (Invited Talk & Embedded Tutorial): Interconnections and Packaging for High Speed and High Frequency PCB/MCM

Session 7A: High-Performance CMOS Circuits

Session 7B: Decision Diagrams

Session 7C: Reconfigurable Systems

Session 7D (Panel Discussion): Asian-Pacific LSI Business in the 21st Century

Session 8A: Testing

Session 8B: Analog CAD

Session 8C: Physical Design for FPGA

Session 8D (Panel & Embedded Tutorial): The Next-Generation System Level Design Language

Session 9A: Analog HDL

Session 9B: System-Level Power Minimization

Session 9C: Floorplannning

Session 9D (Invited Talks): LSI Designs in Multimedia Era

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