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"An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS."
Yung-Hui Chung, Chia-Wei Yen (2017)
- Yung-Hui Chung, Chia-Wei Yen:
An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3434-3443 (2017)
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