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2020 – today
- 2021
[j74]Naoya Onizawa
, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu:
Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access 9: 62890-62898 (2021)- [j73]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - [j72]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 655-665 (2021) - [j71]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 67-76 (2021) - 2020
- [j70]Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8: 188004-188014 (2020) - [j69]Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu:
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7(1): 41-58 (2020) - [j68]Naoya Onizawa, Ren Arakawa, Takahiro Hanyu:
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP 7(1): 89-109 (2020) - [j67]Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1541-1550 (2020) - [j66]Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2171-2181 (2020) - [j65]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu:
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2370-2382 (2020) - [c132]Daisuke Suzuki, Takahiro Hanyu:
Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA. ISMVL 2020: 194-199 - [c131]Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS 2020: 283-286 - [c130]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j64]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [j63]Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu:
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. Microelectron. J. 83: 39-49 (2019) - [j62]Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2263-2274 (2019) - [c129]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. ACSSC 2019: 312-316 - [c128]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS 2019: 115-116 - [c127]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS 2019: 117-118 - [c126]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS 2019: 434-437 - [c125]Tomoki Chiba, Masanori Natsui, Takahiro Hanyu:
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL 2019: 91-96 - [c124]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - 2018
- [j61]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 444-453 (2018) - [j60]Masanori Natsui, Tomoki Chiba, Takahiro Hanyu:
Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. 82: 13-21 (2018) - [j59]Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82: 46-61 (2018) - [j58]Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu:
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2696-2708 (2018) - [j57]Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90(5): 709-725 (2018) - [c123]Daisuke Suzuki, Takahiro Hanyu:
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). FPGA 2018: 291 - [c122]Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. ICECS 2018: 649-650 - [c121]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS 2018: 1-5 - [c120]Hiroki Suda, Masanori Natsui, Takahiro Hanyu:
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL 2018: 56-61 - [c119]Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu:
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL 2018: 156-161 - 2017
- [j56]Takahiro Hanyu:
Foreword. IEICE Trans. Inf. Syst. 100-D(8): 1555 (2017) - [j55]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. 100-D(8): 1592-1602 (2017) - [j54]Daisuke Suzuki, Takahiro Hanyu:
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. IEICE Trans. Inf. Syst. 100-D(8): 1618-1624 (2017) - [j53]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5(2): 151-163 (2017) - [j52]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2688-2699 (2017) - [j51]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2724-2735 (2017) - [c118]Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125 - [c117]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui:
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE 2017: 548-553 - [c116]Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC 2017: 43-46 - [c115]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP 2017: 1315-1319 - [c114]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Evaluation of Stochastic Cascaded IIR Filters. ISMVL 2017: 224-229 - [c113]Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu:
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS 2017: 309-312 - 2016
- [j50]Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross:
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 13-24 (2016) - [j49]Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno:
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 109-119 (2016) - [j48]Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26(1-2): 125-140 (2016) - [j47]Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno:
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c112]Daisuke Suzuki, Takahiro Hanyu:
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. FPL 2016: 1-4 - [c111]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Gammatone filter based on stochastic computation. ICASSP 2016: 1036-1040 - [c110]Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - [c109]Daisuke Suzuki, Takahiro Hanyu:
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. ISMVL 2016: 5-10 - [c108]Naoto Sugaya, Masanori Natsui, Takahiro Hanyu:
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL 2016: 72-77 - [c107]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL 2016: 223-228 - [c106]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI implementation of deep neural networks using integral stochastic computing. ISTC 2016: 216-220 - [c105]Masanori Natsui, Naoto Sugaya, Takahiro Hanyu:
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS 2016: 1-4 - [c104]Naoya Onizawa, Takahiro Hanyu:
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS 2016: 1-4 - 2015
- [j46]Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - [j45]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22(9): 1224-1228 (2015) - [c103]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE 2015: 1006-1011 - [c102]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Frequency-flexible stochastic Gabor filter. DSP 2015: 458-462 - [c101]Akira Mochizuki, Naoto Yube, Takahiro Hanyu:
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON 2015: 3283-3288 - [c100]Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu:
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL 2015: 109-114 - [c99]Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu:
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL 2015: 152-157 - [c98]Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu:
Scaled IIR filter based on stochastic computation. MWSCAS 2015: 1-4 - [c97]Daisuke Suzuki, Takahiro Hanyu:
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure. MWSCAS 2015: 1-4 - [c96]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH 2015: 39-44 - [c95]Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu:
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS 2015: 1-4 - [c94]Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
Stochastic implementation of the disparity energy model for depth perception. SiPS 2015: 1-6 - [c93]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - [i2]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR abs/1509.08972 (2015) - 2014
- [j44]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j43]Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11(3): 20131006 (2014) - [j42]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j41]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [j40]Naoya Onizawa, Takahiro Hanyu:
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. IEICE Electron. Express 11(24): 20141017 (2014) - [j39]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [j38]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. 97-D(9): 2286-2295 (2014) - [j37]Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu:
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. 97-D(9): 2304-2311 (2014) - [j36]Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu:
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers 63(3): 637-649 (2014) - [j35]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 865-876 (2014) - [j34]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. 76(2): 185-194 (2014) - [c92]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - [c91]Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu:
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS 2014: 683-686 - [c90]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC 2014: 1-8 - [c89]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi:
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c88]Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu:
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS 2014: 1865-1868 - [c87]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL 2014: 67-72 - [c86]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL 2014: 208-213 - [c85]Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL 2014: 220-225 - [c84]Masanori Natsui, Takahiro Hanyu:
Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL 2014: 243-247 - [c83]Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi:
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - [c82]Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu:
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH 2014: 59-64 - [c81]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS 2014: 193-196 - [c80]Masanori Natsui, Takahiro Hanyu:
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS 2014: 468 - [c79]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross:
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS 2014: 133-138 - [i1]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR abs/1402.0808 (2014) - 2013
- [j33]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10(7): 20130148 (2013) - [j32]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013) - [j31]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. 96-D(9): 1952-1961 (2013) - [j30]Masanori Natsui, Takahiro Hanyu:
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. 21(5-6): 597-608 (2013) - [c78]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC 2013: 8-15 - [c77]Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi:
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - [c76]Takahiro Hanyu:
Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. ISCAS 2013: 117-120 - [c75]Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu:
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL 2013: 146-151 - [c74]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL 2013: 254-259 - [c73]Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto:
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information. ISMVL 2013: 266-271 - [c72]Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j29]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(6): 1018-1029 (2012) - [j28]Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu:
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. 19(1-3): 219-231 (2012) - [c71]Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476 - [c70]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu:
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC 2012: 41-48 - [c69]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c68]Youngkeun Kim, Masanori Natsui, Takahiro Hanyu:
Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS 2012: 2705-2708 - [c67]