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"Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on ..."

Tao-Tao Zhu et al. (2017)

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DOI: 10.1109/TVLSI.2017.2652482

access: closed

type: Journal Article

metadata version: 2020-03-11

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ZhuMXY17
Tao-Tao Zhu, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1681-1693 (2017)

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