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2020 – today
- 2024
[j7]Bastien Giraud
, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas:
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. IEEE J. Solid State Circuits 59(9): 3045-3057 (2024)- 2023
- [c40]Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Binary ReRAM-based BNN first-layer implementation. DATE 2023: 1-6 - [c39]Bastien Giraud, Sebastien Ricavy, Yasser Moursy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Manuel Pezzin, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas:
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. IMW 2023: 1-4 - [c38]Jean-Philippe Noël, Emanuele Valea, Laurent Grenouillet, B. Chapuis, C. Fisher, A. Recoquillay, Bastien Giraud:
Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems. VLSI-SoC 2023: 1-6 - 2022
- [j6]Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel:
Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution. ACM J. Emerg. Technol. Comput. Syst. 18(2): 40:1-40:26 (2022) - [c37]Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-François Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello:
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. IRPS 2022: 8-1 - [c36]A. Philippe, Lorenzo Ciampolini, A. Philippe, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël:
An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. SLIP 2022: 4:1-4:7 - [i2]Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-Francois Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello:
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. CoRR abs/2203.01680 (2022) - 2021
- [c35]Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE 2021: 1-6 - [c34]Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSCIRC 2021: 83-86 - [c33]Jean-Philippe Noel, Manuel Pezzin, Jean-Frédéric Christmann, Lorenzo Ciampolini, M. Le Coadou, M. Diallo, Florent Lepin, B. Blampey, Simone Bacles-Min, R. Wacquez, Bastien Giraud:
A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. ESSCIRC 2021: 455-458 - [c32]Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSDERC 2021: 83-86 - [c31]J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal:
A Self-referenced and regulated sensing solution for PCM with OTS selector. VLSI-SoC 2021: 1-6 - [c30]J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal:
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. VLSI-SoC (Selected Papers) 2021: 225-243 - 2020
- [c29]Valentin Gherman, Samuel Evain, Bastien Giraud:
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. DATE 2020: 298-301 - [c28]Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud:
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE 2020: 1187-1192 - [c27]Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles:
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. ISLPED 2020: 121-126 - [i1]Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu:
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR abs/2012.00061 (2020)
2010 – 2019
- 2019
- [c26]Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn:
RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS 2019: 34-47 - 2018
- [j5]Alessandro Grossi, Elisa Vianello, Cristian Zambelli, Pablo Royer, Jean-Philippe Noel, Bastien Giraud, Luca Perniola, Piero Olivo, Etienne Nowak:
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2599-2607 (2018) - [c25]Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel:
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces. DATE 2018: 1634-1639 - [c24]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS 2018: 1-6 - [c23]Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné:
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. NANOARCH 2018: 131-137 - [c22]Ian O'Connor, Mayeul Cantan, Cédric Marchand, Bertrand Vilquin, Stefan Slesazeck, Evelyn T. Breyer, Halid Mulaosmanovic, Thomas Mikolajick, Bastien Giraud, Jean-Philippe Noel, Adrian M. Ionescu, Igor Stolichnov:
Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. VLSI-SoC 2018: 180-183 - [c21]Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel:
Reliable ReRAM-based Logic Operations for Computing in Memory. VLSI-SoC 2018: 192-195 - 2017
- [j4]Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi:
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [j3]Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Melanie Brocard, David Turgis, Edith Beigné:
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2296-2306 (2017) - [c20]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - [c19]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
High density emerging resistive memories: What are the limits? LASCAS 2017: 1-4 - [c18]Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
Architecture, design and technology guidelines for crosspoint memories. NANOARCH 2017: 55-60 - [c17]Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noël:
Software platform dedicated for in-memory computing circuit evaluation. RSP 2017: 43-49 - 2016
- [c16]Kaya Can Akyel, Henri-Pierre Charles, Julien Mottin, Bastien Giraud, Gregory Suraci, Sébastien Thuries, Jean-Philippe Noel:
DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture. ICRC 2016: 1-8 - [c15]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal:
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH 2016: 7-12 - 2015
- [j2]Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart:
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c14]Anuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor R. Parthasarathy, Jean-Philippe Noel, David Turgis, Bastien Giraud, Guillaume Moritz:
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT 2015: 1-4 - [c13]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS 2015: 1-4 - 2014
- [c12]Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack:
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c11]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson:
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c10]Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover:
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. ICICDT 2013: 53-56 - [c9]Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC 2013: 424-425 - [c8]Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné:
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC 2013: 168-173 - 2011
- [j1]Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos:
Technology Variability From a Design Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 1996-2009 (2011) - 2010
- [c7]Borivoje Nikolic, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Ji-Hoon Park, Seng Oon Toh:
Technology variability from a design perspective. CICC 2010: 1-8 - [c6]Amara Amara, Bastien Giraud, Olivier Thomas:
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. DELTA 2010: 241-244
2000 – 2009
- 2009
- [c5]Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara:
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. ISCAS 2009: 3170-3173 - 2008
- [c4]Bastien Giraud, Amara Amara:
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. DELTA 2008: 201-204 - [c3]Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara:
An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. ICECS 2008: 554-557 - [c2]Bastien Giraud, Amara Amara:
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. ISCAS 2008: 1906-1909 - 2007
- [c1]Bastien Giraud, Amara Amara, Andrei Vladimirescu:
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. ISCAS 2007: 3022-3025
Coauthor Index
aka: Jean-Philippe Noel
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