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"Delay Analysis for Current Mode Threshold Logic Gate Designs."
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas (2017)
- Chandra Babu Dara
, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1063-1071 (2017)
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