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2020 – today
- 2025
[j7]Archit Joshi
:
Nonlinearity Analysis of Down-Sampled Paths in High-Speed ADC-Based SerDes Receivers. IEEE Access 13: 38698-38703 (2025)- [i1]Aadi Srivastava, Vignesh Natarajkumar, Utkarsh Bheemanaboyna, Devisree Akashapu, Nagraj Gaonkar, Archit Joshi:
VERITAS: Verification and Explanation of Realness in Images for Transparency in AI Systems. CoRR abs/2507.05146 (2025) - 2024
- [j6]Archit Joshi:
Data Path Nonlinearity Estimation for 200 Gbps PAM4 Serdes Receivers. IEEE Access 12: 82842-82847 (2024)
2010 – 2019
- 2019
- [j5]Archit Joshi, Mukul Sarkar:
An Odd Phase CDR With Phase Interpolator Trimming. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 31-35 (2019) - [j4]Archit Joshi, Mukul Sarkar:
A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1790-1798 (2019) - 2017
- [j3]Archit Joshi, Mukul Sarkar:
Nonlinearity Estimation for Compensation of Phase Interpolator in Bang-Bang CDRs. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 388-392 (2017) - 2016
- [j2]Archit Joshi, Gagan Midha:
Bandwidth Compensation Technique for Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1044-1048 (2016) - 2015
- [j1]Archit Joshi:
Period Jitter of Frequency-Locked Loops. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1534-1546 (2015)
2000 – 2009
- 2008
- [c1]Archit Joshi:
Analysis of Bang-bang CDR circuits with equations of linear motion. ICECS 2008: 1143-1146
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