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ORCIDBenjamin Carrión Schäfer
Benjamin Carrion Schafer
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- affiliation: Hong Kong Polytechnic University
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2020 – today
- 2024
[j35]Qilin Si
, Benjamin Carrion Schafer:
MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors. Microprocess. Microsystems 106: 105039 (2024)- [c76]Benjamin Carrion Schafer, Chaitali G. Sathe:
Circumventing Restrictions in Commercial High-Level Synthesis Tools. DATE 2024: 1-2 - 2023
- [j34]Tejinder Kaur, Axel Gamez, José Luis Olvera-Cervantes, Benjamin Carrión Schäfer, Alonso Corona-Chavez:
I-TAINTED: Identification of Turmeric Adulteration Using the CavIty PerturbatioN Technique and Technology OptimizED Machine Learning. IEEE Access 11: 66456-66466 (2023) - [j33]Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia:
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. Integr. 88: 116-124 (2023) - [j32]Md. Imtiaz Rashid, Benjamin Carrion Schafer:
Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3939-3950 (2023) - [j31]Qilin Si, Prattay Chowdhury, Rohit Sreekumar, Benjamin Carrion Schafer:
Application Specific Approximate Behavioral Processor. IEEE Trans. Sustain. Comput. 8(2): 165-179 (2023) - [c75]Prattay Chowdhury, Jorge Castro-Godínez, Benjamin Carrion Schafer:
Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks. ASP-DAC 2023: 410-415 - [c74]Md. Imtiaz Rashid, Benjamin Carrion Schafer:
MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR. DATE 2023: 1-6 - [c73]Chaitali Sathe, Yiorgos Makris, Benjamin Carrion Schafer:
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS. DATE 2023: 1-6 - [c72]Qilin Si, Benjamin Carrión Schäfer:
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing. ACM Great Lakes Symposium on VLSI 2023: 23-28 - [c71]Qilin Si, Benjamin Carrión Schäfer:
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors. ACM Great Lakes Symposium on VLSI 2023: 327-332 - [c70]M. Imtiaz Rashid, Amir H. Torabi, Benjamin Carrión Schäfer:
CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis. ISCAS 2023: 1-5 - 2022
- [j30]Zi Wang, Benjamin Carrion Schafer:
SSSL: Secure Search Space Locking of Behavioral IPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1868-1877 (2022) - [j29]Prattay Chowdhury, Benjamin Carrión Schäfer:
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control. ACM Trans. Design Autom. Electr. Syst. 27(2): 14:1-14:18 (2022) - [j28]Zi Wang, Benjamin Carrion Schafer:
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs. ACM Trans. Design Autom. Electr. Syst. 27(4): 34:1-34:23 (2022) - [c69]Qilin Si, Benjamin Carrion Schafer:
Optimizing Behavioral Near On-Chip Memory Computing Systems. ASAP 2022: 27-33 - [c68]M. Imtiaz Rashid, Benjamin Carrión Schäfer:
Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. ASP-DAC 2022: 623-628 - [c67]Benjamin Carrión Schäfer:
Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling. ASP-DAC 2022: 629-634 - [c66]M. Imtiaz Rashid, Benjamin Carrion Schafer:
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration. ACM Great Lakes Symposium on VLSI 2022: 85-90 - [c65]Md. Imtiaz Rashid, Qilin Si, Benjamin Carrión Schäfer:
Modernizing Hardware Circuits through High-Level Synthesis. ISCAS 2022: 1739-1743 - [c64]Prattay Chowdhury, Chaitali Sathe, Benjamin Carrión Schäfer:
Predictive Model Attack for Embedded FPGA Logic Locking. ISLPED 2022: 32:1-32:6 - [p1]Nandeesha Veeranna, Benjamin Carrion Schafer:
Source Code Obfuscation of Behavioral IPs: Challenges and Solutions. Behavioral Synthesis for Hardware Security 2022: 43-56 - 2021
- [c63]Jianqi Chen, Benjamin Carrión Schäfer:
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. ASP-DAC 2021: 542-547 - [c62]Santosh Shetty, Benjamin Carrión Schäfer:
Enabling the Design of Behavioral Systems-on-Chip. DAC 2021: 331-336 - [c61]Zi Wang, Benjamin Carrión Schäfer:
Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions. DATE 2021: 42-45 - [c60]Jianqi Chen, Benjamin Carrión Schäfer:
Watermarking of Behavioral IPs: A Practical Approach. DATE 2021: 1266-1271 - [c59]Prattay Chowdhury, Benjamin Carrión Schäfer:
Unlocking Approximations through Selective Source Code Transformations. ACM Great Lakes Symposium on VLSI 2021: 359-364 - [c58]Prattay Chowdhury, Benjamin Carrión Schäfer:
Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing. ICCD 2021: 1-4 - [c57]Zi Wang, Shayan Omais Mohammed, Yiorgos Makris, Benjamin Carrión Schäfer:
Functional Locking through Omission: From HLS to Obfuscated Design. ICCD 2021: 591-598 - [c56]Yiheng Gao, Benjamin Carrión Schäfer:
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation. ISCAS 2021: 1-5 - [c55]Zhiqi Zhu, Benjamin Carrión Schäfer:
Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing. ISCAS 2021: 1-5 - [c54]Prattay Chowdhury, Benjamin Carrión Schäfer:
BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs. ISLPED 2021: 1-6 - [c53]Qilin Si, M. Imtiaz Rashid, Benjamin Carrión Schäfer:
Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support. ISVLSI 2021: 212-217 - [c52]Pandy Kalimuthu, Kanad Basu, Benjamin Carrión Schäfer:
Efficient Hierarchical Post-Silicon Validation and Debug. VLSID 2021: 258-263 - 2020
- [j27]Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer:
Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2615-2627 (2020) - [j26]Benjamin Carrión Schäfer, Zi Wang:
High-Level Synthesis Design Space Exploration: Past, Present, and Future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2628-2639 (2020) - [c51]Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer:
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. DAC 2020: 1-6 - [c50]Zi Wang, Benjamin Carrión Schäfer:
Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration. DAC 2020: 1-6 - [c49]Zi Wang, Jianqi Chen, Benjamin Carrión Schäfer:
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization. DATE 2020: 145-150 - [c48]Siyuan Xu, Benjamin Carrión Schäfer:
On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations. DATE 2020: 1378-1383 - [c47]Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen:
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. DATE 2020: 1526-1531 - [c46]Rohit Sreekumar, Prattay Chowdhury, Benjamin Carrión Schäfer:
Bespoke Behavioral Processors. ICCD 2020: 336-339 - [c45]Zhiqi Zhu, Benjamin Carrión Schäfer:
Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis. ISCAS 2020: 1-5 - [c44]Anjana Balachandran, Benjamin Carrión Schäfer:
Efficient Functional Locking of Behavioral IPs. MWSCAS 2020: 639-642
2010 – 2019
- 2019
- [j25]David Aledo, Benjamin Carrión Schäfer, Félix Moreno:
VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks. IEICE Trans. Inf. Syst. 102-D(3): 512-521 (2019) - [j24]Anushree Mahapatra, Benjamin Carrión Schäfer:
VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration. Integr. 64: 1-12 (2019) - [j23]Siyuan Xu, Shuangnan Liu, Yidi Liu, Anushree Mahapatra, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer:
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. Microprocess. Microsystems 65: 169-179 (2019) - [j22]Siyuan Xu, Benjamin Carrión Schäfer:
Toward Self-Tunable Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 778-789 (2019) - [c43]Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer:
Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration. DAC 2019: 97 - [c42]Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer, Carl Sechen, Yiorgos Makris:
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. DATE 2019: 528-533 - [c41]Zi Wang, Benjamin Carrión Schäfer:
Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis. DATE 2019: 642-645 - [c40]Farah Naz Taher, Matthew Joslin, Anjana Balachandran, Zhiqi Zhu, Benjamin Carrión Schäfer:
Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis. DATE 2019: 1563-1566 - [c39]Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer:
Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures. FCCM 2019: 267-270 - [c38]Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen:
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. ACM Great Lakes Symposium on VLSI 2019: 171-176 - [c37]Zhiqi Zhu, Farah Naz Taher, Benjamin Carrión Schäfer:
Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators. ACM Great Lakes Symposium on VLSI 2019: 291-294 - [c36]Jianqi Chen, Benjamin Carrión Schäfer:
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis. ACM Great Lakes Symposium on VLSI 2019: 331-334 - [c35]Siyuan Xu, Benjamin Carrión Schäfer:
Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models. ICCAD 2019: 1-8 - [c34]Jianqi Chen, Benjamin Carrión Schäfer:
Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation. ICCD 2019: 359-366 - [c33]Jianqi Chen, Benjamin Carrión Schäfer:
Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design. ICCD 2019: 401-404 - [c32]Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer:
Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure. ICCD 2019: 460-467 - [c31]Siyuan Xu, Benjamin Carrión Schäfer:
Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations. ICCD 2019: 524-531 - [c30]Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen:
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. FPT 2019: 291-294 - [c29]Anushree Mahapatra, Benjamin Carrión Schäfer:
Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration. ISCAS 2019: 1-5 - 2018
- [j21]Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer:
Accelerating cycle-accurate system-level simulations through behavioral templates. Integr. 62: 282-291 (2018) - [c28]Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer:
A machine learning based hard fault recuperation model for approximate hardware accelerators. DAC 2018: 80:1-80:6 - [c27]Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer:
Investigation and Optimization of Pin Multiplexing in High-Level Synthesis. ACM Great Lakes Symposium on VLSI 2018: 427-430 - [c26]Siyuan Xu, Benjamin Carrión Schäfer:
Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles. ICCD 2018: 346-349 - [c25]Siyuan Xu, Benjamin Carrión Schäfer:
DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures. ICCD 2018: 587-594 - [c24]Farah Naz Taher, Mostafa Kishani, Benjamin Carrión Schäfer:
Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis. IOLTS 2018: 232-235 - [c23]Zhiqi Zhu, Joseph Callenes-Sloan, Benjamin Carrión Schäfer:
Control Flow Checking Optimization Based on Regular Patterns Analysis. PRDC 2018: 203-212 - 2017
- [j20]Nandeesha Veeranna, Benjamin Carrión Schäfer:
Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs. J. Hardw. Syst. Secur. 1(1): 56-67 (2017) - [j19]Nandeesha Veeranna, Benjamin Carrión Schäfer:
S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis. J. Hardw. Syst. Secur. 1(2): 103-113 (2017) - [j18]Benjamin Carrión Schäfer:
Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 97-105 (2017) - [j17]Nandeesha Veeranna, Benjamin Carrión Schäfer:
Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques. IEEE Trans. Emerg. Top. Comput. 5(4): 576-585 (2017) - [j16]Benjamin Carrión Schäfer:
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies. ACM Trans. Design Autom. Electr. Syst. 22(4): 65:1-65:20 (2017) - [j15]Siyuan Xu, Benjamin Carrión Schäfer:
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3077-3088 (2017) - [c22]Benjamin Carrión Schäfer, David Aledo, Félix Moreno:
Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study. DSD 2017: 129-136 - [c21]Shuangnan Liu, Benjamin Carrión Schäfer:
Learning-based interconnect-aware dataflow accelerator optimization. FPL 2017: 1-7 - [c20]Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran:
What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI 2017: 351-356 - [c19]Siyuan Xu, Benjamin Carrión Schäfer:
Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads. ICCD 2017: 113-120 - [c18]Siyuan Xu, Benjamin Carrión Schäfer, Yidi Liu:
Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration. ICCD 2017: 509-512 - [c17]Nandeesha Veeranna, Benjamin Carrión Schäfer:
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. LATS 2017: 1-6 - [c16]Siyuan Xu, Jianqi Chen, Benjamin Carrión Schäfer:
HW/SW co-design experimental framework using configurable SoCs. ReConFig 2017: 1-6 - [c15]Yidi Liu, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer:
Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. ReCoSoC 2017: 1-8 - 2016
- [j14]Benjamin Carrión Schäfer:
Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 394-406 (2016) - [j13]Benjamin Carrión Schäfer:
Source Code Error Detection in High-Level Synthesis Functional Verification. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 301-312 (2016) - [j12]Benjamin Carrión Schäfer:
Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 324-328 (2016) - [c14]Yidi Liu, Benjamin Carrión Schäfer:
Optimization of behavioral IPs in multi-processor system-on-chips. ASP-DAC 2016: 336-341 - [c13]Dong Liu, Benjamin Carrión Schäfer:
Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. FPL 2016: 1-8 - [c12]Nandeesha Veeranna, Benjamin Carrión Schäfer:
Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs. FPT 2016: 193-196 - [c11]Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer:
On Time Redundancy of Fault Tolerant C-Based MPSoCs. ISVLSI 2016: 631-636 - [i1]Jieshi Chen, Benjamin Carrión Schäfer, Ivan Wang Hei Ho:
Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring. CoRR abs/1603.06669 (2016) - 2015
- [j11]Benjamin Carrión Schäfer:
Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support. IEEE Embed. Syst. Lett. 7(2): 51-54 (2015) - [c10]Xiaotong Li, Benjamin Carrión Schäfer:
Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. FPL 2015: 1-4 - 2014
- [j10]Benjamin Carrión Schäfer, Anushree Mahapatra:
S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis. IEEE Embed. Syst. Lett. 6(3): 53-56 (2014) - [c9]Benjamin Carrión Schäfer:
Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. ASP-DAC 2014: 616-621 - [c8]Benjamin Carrión Schäfer:
Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systems. FPT 2014: 76-82 - [c7]Yidi Liu, Benjamin Carrión Schäfer:
HW acceleration of multiple applications on a single FPGA. FPT 2014: 284-285 - 2012
- [j9]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Machine learning predictive modelling high-level synthesis design space exploration. IET Comput. Digit. Tech. 6(3): 153-159 (2012) - [j8]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Divide and conquer high-level synthesis design space exploration. ACM Trans. Design Autom. Electr. Syst. 17(3): 29:1-29:19 (2012) - 2011
- [j7]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Precision tunable RTL macro-modelling cycle-accurate power estimation. IET Comput. Digit. Tech. 5(2): 95-103 (2011) - 2010
- [j6]Benjamin Carrión Schäfer, Yusuke Iguchi, Wataru Takahashi, Shingo Nagatani, Kazutoshi Wakabayashi:
Fixed Point Data Type Modeling for High Level Synthesis. IEICE Trans. Electron. 93-C(3): 361-368 (2010) - [j5]Benjamin Carrion Schafer, Majid Sarrafzadeh:
Semi-Automatic Control Unit Generation for Complex VLSI Designs. Inf. Media Technol. 5(4): 1122-1131 (2010) - [j4]Benjamin Carrión Schäfer, Majid Sarrafzadeh:
Semi-Automatic Control Unit Generation for Complex VLSI Designs. IPSJ Trans. Syst. LSI Des. Methodol. 3: 234-243 (2010) - [j3]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Design Space Exploration Acceleration Through Operation Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 153-157 (2010) - [c6]Benjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi:
Design of complex image processing systems in ESL. ASP-DAC 2010: 809-814 - [c5]Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum:
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED 2010: 49-54
2000 – 2009
- 2009
- [j2]Benjamin Carrión Schäfer, Taewhan Kim:
Autonomous temperature control technique in VLSI circuits through logic replication. IET Comput. Digit. Tech. 3(1): 62-71 (2009) - 2008
- [j1]Benjamin Carrión Schäfer, Taewhan Kim:
Hotspots Elimination and Temperature Flattening in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1475-1487 (2008) - 2007
- [c4]Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim:
Temperature-Aware Compilation for VLIWProcessors. RTCSA 2007: 426-431 - 2003
- [b1]Benjamin Carrión Schäfer:
Acceleration of the discrete element method on a reconfigurable co-processor. University of Birmingham, UK, 2003 - 2002
- [c3]Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. FCCM 2002: 173-181 - [c2]Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. FPL 2002: 925-934 - 2001
- [c1]Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
Evaluation of an FPGA Implementation of the Discrete Element Method. FPL 2001: 306-314
Coauthor Index
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