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ORCIDManuel Valencia-Barrero
Person information
- affiliation: Czech Technical University in Prague, Department of Circuit Theory, Czech Republic
Other persons with the same name
- Manuel Valencia — disambiguation page
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Journal Articles
- 2021
[j12]Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez
, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández:
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access 9: 168444-168454 (2021)- [j11]Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández:
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. Sensors 21(22): 7596 (2021) - 2020
- [j10]Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero:
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. 15(3): 123-128 (2020) - [j9]Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández:
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors 20(23): 6909 (2020) - [j8]José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Trans. Circuits Syst. 67-II(11): 2682-2686 (2020) - 2017
- [j7]José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Trivium hardware implementations for power reduction. Int. J. Circuit Theory Appl. 45(2): 188-198 (2017) - [j6]Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Vulnerability Analysis of Trivium FPGA Implementations. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3380-3389 (2017) - [j5]José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Multiradix Trivium Implementations for Low-Power IoT Hardware. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3401-3405 (2017) - 2005
- [j4]Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero:
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1(1): 11-19 (2005) - 1995
- [j3]Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas:
SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits 30(7): 835-838 (1995) - [j2]Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano:
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995) - 1986
- [j1]J. Calvo, José I. Acha, Manuel Valencia-Barrero:
Asynchronous Modular Arbiter. IEEE Trans. Computers 35(1): 67-70 (1986)
Conference and Workshop Papers
- 2020
- [c18]Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández:
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. ISCAS 2020: 1-5 - 2018
- [c17]Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero:
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS 2018: 1-6 - 2016
- [c16]Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Fault attack on FPGA implementations of Trivium stream cipher. ISCAS 2016: 562-565 - 2012
- [c15]José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Low Power Implementation of Trivium Stream Cipher. PATMOS 2012: 113-120 - 2007
- [c14]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD 2007: 156-159 - [c13]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896 - 2002
- [c12]Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia:
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS 2002: 353-362 - [c11]Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero:
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457 - 2001
- [c10]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero:
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471 - [c9]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia:
AUTODDM: automatic characterization tool for the delay degradation model. ICECS 2001: 1631-1634 - [c8]Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486 - 2000
- [c7]Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462 - [c6]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158 - [c5]Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero:
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326 - 1998
- [c4]Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia:
Efficient self-timed circuits based on weak NMOS-trees. ICECS 1998: 179-182 - 1995
- [c3]Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23 - 1993
- [c2]Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas:
Modeling of real bistables in VHDL. EURO-DAC 1993: 460-465 - [c1]Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro:
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022
Parts in Books or Collections
- 2008
- [p1]Angel Barriga, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Logic Synthesis. Wiley Encyclopedia of Computer Science and Engineering 2008
Coauthor Index
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