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"ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric ..."

Po-Hao Wang et al. (2017)

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DOI: 10.1109/TVLSI.2016.2642170

access: closed

type: Journal Article

metadata version: 2020-03-11

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  dblp key:
  - journals/tvlsi/WangCTLTLSLWC17
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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/WangCTLTLSLWC17
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3341-3354 (2017)

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