default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDV. Kamakoti 0001
Kamakoti Veezhinathan – Veezhinathan Kamakoti
Person information
- affiliation: Indian Institute of Technology Madras, India
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2025
[j52]Sareena Karapoola
, Nikhilesh Singh, Chester Rebeiro, Kamakoti Veezhinathan:
SUNDEW: A Case-Sensitive Detection Engine to Counter Malware Diversity. IEEE Trans. Dependable Secur. Comput. 22(1): 518-533 (2025)- 2024
- [j51]Kaushik Raghavan, Sivaselvan Balasubramanian, Kamakoti Veezhinathan:
Explainable artificial intelligence for medical imaging: Review and experiments with infrared breast images. Comput. Intell. 40(3) (2024) - 2023
- [j50]Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti:
Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. IEEE Trans. Dependable Secur. Comput. 20(5): 3734-3752 (2023) - [c85]Sandip Saha, Sareena Karapoola, Chester Rebeiro, V. Kamakoti:
YODA: Covert Communication Channel over Public DNS Resolvers. DSN 2023: 252-260 - [c84]Kaushik Raghavan, B. Sivaselavan, V. Kamakoti:
iPyrDAE: Image Pyramid-Based Denoising Autoencoder for Infrared Breast Images. PReMI 2023: 397-406 - 2022
- [j49]Kamakoti Veezhinathan:
Building the SHAKTI microprocessor. Commun. ACM 65(11): 48-51 (2022) - [j48]Prasanna Karthik Vairam, Pratyush Kumar, Chester Rebeiro, V. Kamakoti:
FadingBF: A Bloom Filter With Consistent Guarantees for Online Applications. IEEE Trans. Computers 71(1): 40-52 (2022) - [c83]Sareena Karapoola, Nikhilesh Singh, Chester Rebeiro, V. Kamakoti:
RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks. CIKM 2022: 3222-3232 - [c82]Sareena Karapoola, Nikhilesh Singh, Chester Rebeiro, Kamakoti Veezhinathan:
JUGAAD: Comprehensive Malware Behavior-as-a-Service. CSET @ USENIX Security Symposium 2022: 39-48 - [i4]Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti:
Snoopy: A Webpage Fingerprinting Framework with Finite Query Model for Mass-Surveillance. CoRR abs/2205.15037 (2022) - 2021
- [j47]Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti:
PERI: A Configurable Posit Enabled RISC-V Core. ACM Trans. Archit. Code Optim. 18(3): 25:1-25:26 (2021) - 2020
- [j46]Rahul Bodduna, Vinod Ganesan, Patanjali SLPSK, Kamakoti Veezhinathan, Chester Rebeiro:
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER. IEEE Comput. Archit. Lett. 19(1): 9-12 (2020) - [j45]Sareena Karapoola, Prasanna Karthik Vairam, Shankar Raman, Veezhinathan Kamakoti:
Net-Police: A network patrolling service for effective mitigation of volumetric DDoS attacks. Comput. Commun. 150: 438-454 (2020) - [j44]Milan Patnaik, G. Prabhu, Chester Rebeiro, Vashek Matyas, Kamakoti Veezhinathan:
ProBLeSS: A Proactive Blockchain Based Spectrum Sharing Protocol Against SSDF Attacks in Cognitive Radio IoBT Networks. IEEE Netw. Lett. 2(2): 67-70 (2020) - [j43]Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri:
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. IET Comput. Digit. Tech. 14(3): 122-131 (2020) - [c81]Sudhakar Murugasen, Shankar Raman, Kamakoti Veezhinathan:
VNF-DOC: A Dynamic Overload Controller for Virtualized Network Functions in Cloud. AINA 2020: 642-656 - [c80]Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan:
Sparsity-Aware Caches to Accelerate Deep Neural Networks. DATE 2020: 85-90 - [c79]Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan:
Depending on HTTP/2 for Privacy? Good Luck! DSN 2020: 278-285
2010 – 2019
- 2019
- [j42]Milan Patnaik, V. Kamakoti, Vashek Matyas, Vojtech Rehák:
PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks. IEEE Trans. Cogn. Commun. Netw. 5(2): 400-412 (2019) - [c78]Sareena Karapoola, Chester Rebeiro, Unnati Parekh, Kamakoti Veezhinathan:
Towards Identifying Early Indicators of a Malware Infection. AsiaCCS 2019: 679-681 - [c77]Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti:
Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. ICCAD 2019: 1-8 - [c76]Prasanna Karthik Vairam, Gargi Mitra, Vignesh Manoharan, Chester Rebeiro, Byrav Ramamurthy, Kamakoti Veezhinathan:
Towards Measuring Quality of Service in Untrusted Multi-Vendor Service Function Chains: Balancing Security and Resource Consumption. INFOCOM 2019: 163-171 - [c75]Sourav Das, R. Harikrishnan Unnithan, Arjun Menon, Chester Rebeiro, Kamakoti Veezhinathan:
SHAKTI-MS: a RISC-V processor for memory safety in C. LCTES 2019: 19-32 - [c74]Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan:
White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. SIGCOMM Posters and Demos 2019: 122-124 - [i3]Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan:
White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. CoRR abs/1903.06475 (2019) - [i2]Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti:
PERI: A Posit Enabled RISC-V Core. CoRR abs/1908.01466 (2019) - 2018
- [j41]Prasanna Karthik Vairam, Gargi Mitra, Chester Rebeiro, Byrav Ramamurthy, Kamakoti Veezhinathan:
ApproxBC: Blockchain Design Alternatives for Approximation-Tolerant Resource-Constrained Applications. IEEE Commun. Stand. Mag. 2(3): 45-51 (2018) - [j40]Gnanambikai Krishnakumar, Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, Kamakoti Veezhinathan:
GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks. IEEE Embed. Syst. Lett. 10(3): 83-86 (2018) - [j39]Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti:
An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. ACM J. Emerg. Technol. Comput. Syst. 14(1): 1:1-1:28 (2018) - [j38]Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti:
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. J. Low Power Electron. 14(2): 285-301 (2018) - 2017
- [j37]Satya Trinadh Adireddy, Seetal Potluri, Ch. Sobhan Babu, Veezhinathan Kamakoti, Shiv Govind Singh:
Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing. ACM Trans. Design Autom. Electr. Syst. 23(1): 5:1-5:26 (2017) - [j36]Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti:
Approximate Error Detection With Stochastic Checkers. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2258-2270 (2017) - [c73]Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri:
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. DFT 2017: 1-4 - [c72]Arjun Menon, Subadra Murugan, Chester Rebeiro, Neel Gala, Kamakoti Veezhinathan:
Shakti-T: A RISC-V Processor with Light Weight Security Extensions. HASP@ISCA 2017: 2:1-2:8 - [c71]Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, Anand Raghunathan:
A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks. ISLPED 2017: 1-6 - 2016
- [j35]N. Sathya Narayanan, Milan Patnaik, V. Kamakoti:
ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks. Comput. Commun. 93: 27-38 (2016) - [j34]Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay, Kamakoti Veezhinathan:
Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures. J. Low Power Electron. 12(2): 99-106 (2016) - [c70]Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan:
Component fault localization using switching current measurements. ETS 2016: 1-2 - [c69]Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti:
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. ISLPED 2016: 266-271 - [c68]Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti:
SHAKTI Processors: An Open-Source Hardware Initiative. VLSID 2016: 7-8 - [c67]Vikas Chauhan, Neel Gala, V. Kamakoti:
ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. VLSID 2016: 499-504 - [e1]Indrajit Ray, Manoj Singh Gaur, Mauro Conti, Dheeraj Sanghi, V. Kamakoti:
Information Systems Security - 12th International Conference, ICISS 2016, Jaipur, India, December 16-20, 2016, Proceedings. Lecture Notes in Computer Science 10063, Springer 2016, ISBN 978-3-319-49805-8 [contents] - 2015
- [j33]L. Srivani, N. H. V. Krishna Giri, Shankar Ganesh, V. Kamakoti:
Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization. Appl. Soft Comput. 27: 179-190 (2015) - [j32]Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti:
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12(3): 22:1-22:25 (2015) - [j31]Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti:
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11(2): 133-148 (2015) - [j30]Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan:
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. 21(1): 14:1-14:25 (2015) - [c66]Sukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti:
SHAKTI-F: A Fault Tolerant Microprocessor Architecture. ATS 2015: 163-168 - [c65]Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti:
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. DATE 2015: 836-841 - [c64]Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti:
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSID 2015: 381-386 - 2014
- [j29]K. Shyamala, V. Kamakoti:
ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization. J. Low Power Electron. 10(1): 20-31 (2014) - [j28]Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti:
XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. J. Low Power Electron. 10(1): 107-115 (2014) - [c63]Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti:
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID 2014: 342-347 - 2013
- [j27]Shri K. V. Srinivasan, V. Kamakoti, A. Bhattacharya:
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays. ACM J. Emerg. Technol. Comput. Syst. 9(1): 1:1-1:17 (2013) - [j26]Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti:
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9(2): 207-228 (2013) - [j25]Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti:
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. J. Low Power Electron. 9(2): 264-274 (2013) - [c62]Shankar Raman, Kamakoti Veezhinathan, Balaji Venkat, Gaurav Raina:
Using timers to switch-off TCAM banks in routers. IEEE ANTS 2013: 1-6 - [c61]Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti:
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. ETS 2013: 1 - [c60]Abhijit Pradhan, S. Aswin Shanmugam, Anusha Prakash, Kamakoti Veezhinathan, Hema A. Murthy:
A syllable based statistical text to speech system. EUSIPCO 2013: 1-5 - 2012
- [j24]Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli:
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electr. Comput. Eng. 2012: 537286:1-537286:12 (2012) - [j23]Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti:
Interconnect Aware Test Power Reduction. J. Low Power Electron. 8(4): 516-525 (2012) - [j22]Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti:
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8(5): 684-695 (2012) - [c59]Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan:
The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency. HotPower 2012 - 2011
- [j21]Shoaib Mohammed, Sk. Noor Mahammad, V. Kamakoti:
Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. Appl. Soft Comput. 11(1): 842-854 (2011) - [j20]Karthik Raghavan, V. Kamakoti:
ROSY: recovering processor and memory systems from hard errors. ACM SIGOPS Oper. Syst. Rev. 45(3): 82-84 (2011) - [c58]Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella, Veezhinathan Kamakoti:
Reconstructing Hardware Transactional Memory for Workload Optimized Systems. APPT 2011: 1-15 - [c57]S. Srinivasan, V. Kamakoti, A. Bhattacharya:
Towards Quick Solutions for Generalized Placement Problem. ISED 2011: 106-111 - [c56]M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, Kamakoti Veezhinathan:
A Method for Integrating Network-on-Chip Topologies with 3D ICs. ISVLSI 2011: 60-65 - [c55]Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli:
A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI 2011: 206-211 - [c54]Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti:
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI 2011: 319-320 - 2010
- [j19]Kavish Seth, V. Kamakoti, S. Srinivasan:
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. 56(4): 467-480 (2010) - [j18]Sk. Noor Mahammad, Kamakoti Veezhinathan:
Constructing Online Testable Circuits Using Reversible Logic. IEEE Trans. Instrum. Meas. 59(1): 101-109 (2010) - [c53]Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti:
Impact of Temperature on Test Quality. VLSI Design 2010: 276-281
2000 – 2009
- 2009
- [j17]George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi:
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. 5(1): 58-68 (2009) - [j16]K. Shyamala, J. Vimalkumar, V. Kamakoti:
Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. J. Low Power Electron. 5(4): 429-438 (2009) - [j15]Kunal Korgaonkar, K. George, M. Gautam, V. Kamakoti:
HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. ACM SIGOPS Oper. Syst. Rev. 43(2): 98-99 (2009) - [c52]Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi:
Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design 2009: 97-102 - 2008
- [j14]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4(1): 101-110 (2008) - [j13]Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil:
Automatic Constraint Based Test Generation for Behavioral HDL Models. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 408-421 (2008) - 2007
- [j12]Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A novel approach to the placement and routing problems for field programmable gate arrays. Appl. Soft Comput. 7(1): 455-470 (2007) - [j11]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24(4): 374-384 (2007) - [j10]K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula:
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. J. Low Power Electron. 3(3): 280-292 (2007) - [j9]A. Pavan Kumar, V. Kamakoti, Sukhendu Das:
System-on-programmable-chip implementation for on-line face recognition. Pattern Recognit. Lett. 28(3): 342-349 (2007) - [c51]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE 2007: 534-539 - [c50]Sanjay Burman, Debdeep Mukhopadhyay, Kamakoti Veezhinathan:
LFSR Based Stream Ciphers Are Vulnerable to Power Attacks. INDOCRYPT 2007: 384-392 - [c49]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC 2007: 1-10 - [c48]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC 2007: 1-9 - [c47]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356 - [c46]K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula:
Controllability-driven Power Virus Generation for Digital Circuits. VLSI Design 2007: 407-412 - [c45]K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits. VTS 2007: 35-42 - [c44]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007: 167-172 - [i1]Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti:
FPGA based Agile Algorithm-On-Demand Co-Processor. CoRR abs/0710.4824 (2007) - 2006
- [j8]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam:
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. 2(3): 425-436 (2006) - [j7]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2(3): 464-476 (2006) - [c43]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam:
Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI 2006: 119-122 - [c42]Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design 2006: 507-510 - [c41]Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design 2006: 517-520 - 2005
- [j6]L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti:
Pseudo-online testing methodologies for various components of field programmable gate arrays. Microprocess. Microsystems 29(2-3): 99-119 (2005) - [c40]Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC 2005: 791-794 - [c39]Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
A function generator-based reconfigurable system. ASP-DAC 2005: 905-909 - [c38]E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC 2005: 1200-1203 - [c37]K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil:
A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. Asian Test Symposium 2005: 40-45 - [c36]Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti:
FPGA based Agile Algorithm-On-Demand Co-Processor. DATE 2005: 82-83 - [c35]E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA 2005: 265 - [c34]E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS 2005 - [c33]K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti:
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. VLSI Design 2005: 207-212 - [c32]R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia:
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design 2005: 451-456 - [c31]E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design 2005: 736-741 - [c30]Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti:
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. VLSI Design 2005: 795-798 - 2004
- [c29]A. Manoj Kumar, Jayaram Bobba, V. Kamakoti:
MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. DATE 2004: 922-929 - [c28]A. Manoj Kumar, B. Jayaram, V. Kamakoti:
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. FPGA 2004: 251 - [c27]R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti:
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. FPL 2004: 1185 - [c26]R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti:
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. FPT 2004: 57-64 - [c25]E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan:
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT 2004: 121-128 - [c24]Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti:
A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. ICONIP 2004: 327-332 - [c23]A. Pavan Kumar, Sukhendu Das, V. Kamakoti:
Face Recognition Using Weighted Modular Principle Component Analysis. ICONIP 2004: 362-367 - [c22]A. Pavan Kumar, V. Kamakoti, Sukhendu Das:
An Architecture for Real Time Face Recognition Using WMPCA. ICVGIP 2004: 644-649 - [c21]A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti:
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. IPDPS 2004 - [c20]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. MICAI 2004: 735-745 - [c19]P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam:
A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design 2004: 443-448 - [c18]Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar:
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design 2004: 1071-1076 - 2003
- [c17]L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti:
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. Asian Test Symposium 2003: 262-267 - [c16]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. IEEE Congress on Evolutionary Computation 2003: 1708-1715 - [c15]L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti:
Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL 2003: 1044-1047 - [c14]B. Jayaram, A. Manoj Kumar, V. Kamakoti:
Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. HiPC 2003: 174-183 - [c13]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti:
A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. IICAI 2003: 938-951 - [c12]Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. IPDPS 2003: 184 - [c11]M. Madhu, V. Srinivasa Murty, V. Kamakoti:
Dynamic Coding Technique For Low-Power Data Bus. ISVLSI 2003: 252-253 - [c10]L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh:
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI 2003: 224-232 - 2002
- [c9]Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A novel three phase parallel genetic approach to routing for field programmable gate arrays. FPT 2002: 336-339 - 2001
- [c8]K. Srinathan, C. Pandu Rangan, V. Kamakoti:
Toward Optimal Player Weights in Secure Distributed Protocols. INDOCRYPT 2001: 232-241
1990 – 1999
- 1999
- [j5]V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti:
Adaptive finite element analysis on a parallel and distributed environment. Parallel Comput. 25(12): 1413-1434 (1999) - 1998
- [c7]Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan:
The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. COCOON 1998: 35-44 - [c6]Thorsten Graf, Kamakoti Veezhinathan:
Reducing Simple Polygons to Triangles - A Proof for an Improved Conjecture. ICALP 1998: 130-139 - [c5]Thorsten Graf, Kamakoti Veezhinathan:
An Optimal Algorithm for Computing Vissible Nearest Foreign Neighbors Among Colored Line Segments. SWAT 1998: 59-70 - 1997
- [j4]Thomas Graf, V. Kamakoti:
Sparse Dominance Queries for Many Points in Optimal Time and Space. Inf. Process. Lett. 64(6): 287-291 (1997) - [c4]Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan:
An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions. HiPC 1997: 132-136 - [c3]V. Kamakoti, N. Balakrishnan:
Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. ICPADS 1997: 44-51 - 1995
- [j3]K. Arvind, V. Kamakoti, C. Pandu Rangan:
Efficient Parallel Algorithms for Permutation Graphs. J. Parallel Distributed Comput. 26(1): 116-124 (1995) - [j2]V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan:
An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. Nord. J. Comput. 2(1): 28-40 (1995) - [c2]V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan:
Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. COCOON 1995: 71-80 - 1994
- [c1]P. Jagan Mohan, V. Kamakoti, C. Pandu Rangan:
Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. IFIP Congress (1) 1994: 547-552 - 1992
- [j1]V. Kamakoti, C. Pandu Rangan:
An Optimal Algorithm for Reconstructing a Binary Tree. Inf. Process. Lett. 42(2): 113-115 (1992)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-05-03 01:09 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
