![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
MTDT 2001: San Jose, CA, USA
- 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA. IEEE Computer Society 2001, ISBN 0-7695-1242-9
Memory Design
- G. Harling:
A DRAM Compiler for Fully Optimized Memory Instances. 3-8 - Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee:
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme. 9-12 - Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn:
Design of an Embedded Fully-Depleted SOI SRAM. 13-
Memory BIST
- Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara:
A P1500 Compliant Programable BistShell for Embedded Memories. 21-28 - Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho:
BIST-Based Bitfail Mapping of an Embedded DRAM. 29-
Redundancy and Error Control
- Stella Matarrese, Luca Fasoli:
A Method to Caculate Redundancy Coverage for FLASH Memory. 41-44 - Stefano Gregori
, Guido Torelli, Osama Khouri, Rino Micheloni:
An Error Control Code Scheme for Multilevel Flash Memories. 45-50 - Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An Approach for Evaluation of Redunancy Analysis Algorithms. 51-
Fault Models and Multi-Port SRAM Testing
- Zaid Al-Ars, Ad J. van de Goor:
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. 59-64 - Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers:
Realistic Fault Models and Test Procedures for Multi-Port SRAMs. 65-72 - Farzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby:
A Parallel Approach for Testing Multi-Port Static Random Access Memories. 73-
Verification and Test
- Simon Napper, Dian Yang:
Equivalence Checking a 256MB SDRAM. 85-90 - Xiaoling Sun, Jian Xu, Pieter M. Trouborst:
Testing Carry Logic Modules of SRAM-based FPGAs. 91-98 - Osama Khouri, Stefano Gregori
, Dario Soltesz, Guido Torelli, Rino Micheloni:
Low Output Resistance Charge Pump for Flash Memory Programming. 99-
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.