"IS-FPGA : a new symmetric FPGA architecture with implicit scan."

Michel Renovell et al. (2001)

> Home

Details and statistics

DOI: 10.1109/TEST.2001.966716

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/itc/RenovellFPFZ01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/RenovellFPFZ01
Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.